Search - xilinx system generator

Search - xilinx system generator - List

[Communication] xilinx-qam-demodualater DL : 0: 本应用指南着重探讨了正交调幅 (QAM) 信号的基带解调，特别描述了分数率抽取电路模块的使用。本应用指南也对多相抽取滤波器结构进行了简介，讨论了分数率抽取电路及如何使用Xilinx System Generator 8.1i 实现它，并给出了实现结果。
Update : 2008-10-13 Size : 366.33kb Publisher : sky
[SCM] pingpufx DL : 0: Update : 2025-02-17 Size : 374kb Publisher : 郑坤
[VHDL-FPGA-Verilog] FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR. DL : 0: In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.-In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.
Update : 2025-02-17 Size : 248kb Publisher : gsbnd
[VHDL-FPGA-Verilog] MATLAB_sg_IP DL : 0: 使用MATLAB为System Generator for DSP创建IP-The use of MATLAB for System Generator for DSP to create IP
Update : 2025-02-17 Size : 39kb Publisher : lxd
[matlab] ASK-OOK-FSK-BPSK DL : 0: MATLAB实现ASK, OOK, FSK, BPSK, QPSK, 8PSK调制源代码-Free Source Code for ASK, OOK, FSK, BPSK, QPSK, 8PSK Digital Modulation in FPGAs Xilinx using system generator (ASK, BPSK, FSK, OOK, QPSK)
Update : 2025-02-17 Size : 56kb Publisher : chenkui
[matlab] sysgen_gs DL : 0: Xilinx system generator的上手指南，system generator用于在matlab中使用simulink设计硬件，很方便-guide of system generater by Xilinx
Update : 2025-02-17 Size : 1.61mb Publisher : 王静
[Other] DUC DL : 0: 基于软件无线电的SFF平台，采用Xilinx System Generator实现的数字上变频器-SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter
Update : 2025-02-17 Size : 52kb Publisher : 刘荣毅
[Other] Xilinx-Sys-Gen-quickstart DL : 0: Introduction Setting up the System Generator Tool A Quick Tour of the System Generator System Generator Basic Tutorial-Introduction Setting up the System Generator Tool A Quick Tour of the System Generator System Generator Basic Tutorial
Update : 2025-02-17 Size : 562kb Publisher : bobor
[File Format] Advanced-Xilinx-FPGA DL : 1: Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™ System • Describe the different ISE options available and how they can be used to improve performance • Describe a flow for obtaining timing closure with Advance Timing Constraints • Use FloorPlanner to improve timing • Reduce implementation time with Incremental Design Techniques and Modular Design Techniques • Reduce debugging time with FPGA Editor • On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™ System • Describe the different ISE options available and how they can be used to improve performance • Describe a flow for obtaining timing closure with Advance Timing Constraints • Use FloorPlanner to improve timing • Reduce implementation time with Incremental Design Techniques and Modular Design Techniques • Reduce debugging time with FPGA Editor • On-Chip Verification with ChipScope Pro
Update : 2025-02-17 Size : 10.12mb Publisher : rakesh
[Software Engineering] Xcell68 DL : 0: xilinx system generator example of PID control of a system
Update : 2025-02-17 Size : 4.94mb Publisher : sumit
[DSP program] OFDM_Security DL : 0: This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simulink model 2. initialization file. Software requirements: 1. Matlab, r2007a or later 2. Simulink with DSP and Comm blocksets 3. Xilinx ISE with System Generator for DSP 9.2i or later.
Update : 2025-02-17 Size : 157kb Publisher : 徐滨
[Software Engineering] Mathematical-Operation-of-image-pixel-using-XSG.r DL : 0: mathematical opering using xilinx system generator
Update : 2025-02-17 Size : 559kb Publisher : anil
[VHDL-FPGA-Verilog] SGvga DL : 0: 基于System Generator 实现Xilinx FGPA的VGA显示模块，板块Nexys™ 3 Spartan-6 FPGA Board，可以直接把.bit文件下进去进行。具体说明可以参考本人博客：http://www.openhw.org/wenlong0601/blog/12-03/239390_f7ef3.html-Based on the System Generator Xilinx FGPA VGA display module, the plate Nexys ™ 3 the Spartan-6 FPGA Board directly. Bit file into the conduct.
Update : 2025-02-17 Size : 1.17mb Publisher : 张文龙
[VHDL-FPGA-Verilog] cordicsg DL : 0: Xilinx system generator design of CORDIC
Update : 2025-02-17 Size : 20kb Publisher : girish
[VHDL-FPGA-Verilog] BPSK DL : 0: Binary phase shift keying in Xilinx system generator
Update : 2025-02-17 Size : 21kb Publisher : girish
[matlab] Smoothing DL : 0: Xilinx System Generator : Smoothing
Update : 2025-02-17 Size : 47kb Publisher : ossang
[Documents] lab1 DL : 0: labs of system generator lab 1:Using Simulink Lab
Update : 2025-02-17 Size : 181kb Publisher : mohsaber
[VHDL-FPGA-Verilog] lab2 DL : 0: lab 2:Getting Started with Xilinx System Generator
Update : 2025-02-17 Size : 192kb Publisher : mohsaber
[VHDL-FPGA-Verilog] lab3 DL : 0: lab 3 system generator : Signal Routing
Update : 2025-02-17 Size : 76kb Publisher : mohsaber
[Software Engineering] lab4 DL : 0: xilinx system genaerator lab 4
Update : 2025-02-17 Size : 142kb Publisher : mohsaber

« 12 3 »