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[Other] 7seg

Description: 七段数码显示程序 VHDL 开发环境为Xilinx 的集成开发工具ISE-VHDL digital display program development environment for Xilinx ISE Integrated Development Tools
Platform: | Size: 1024 | Author: imljg | Hits:

[Software Engineering] xilinxFPGAdesign

Description: 通过ISE7.0介绍xilinxFPGA设计工具的使用.-ISE7.0 introduction xilinxFPGA through the use of design tools.
Platform: | Size: 1735680 | Author: hogan | Hits:

[Other] ChipScopeTutorial

Description:
Platform: | Size: 1733632 | Author: liu gang | Hits:

[VHDL-FPGA-Verilog] ise

Description: FPGA/CPLD设计工具---Xilinx ISE使用详解光盘源代码，Xilinx公司推荐的FPGA/CPLD培训教材-FPGA/CPLD design tools-Xilinx ISE explain the use of CD-ROM source code, Xilinx Inc. recommended FPGA/CPLD training materials
Platform: | Size: 22214656 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Xilinx可编程逻辑器件的高级应用与设计技巧 全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to Xilinx s CoolRunnerII Spartan-3 Virtex-II VirtexII pro, such as the structural characteristics of the device, as well as its ISE6-aided design tools.
Platform: | Size: 41021440 | Author: 胡赟星 | Hits:

[VHDL-FPGA-Verilog] FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.

Description: In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.-In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.
Platform: | Size: 253952 | Author: gsbnd | Hits:

[uCOS] Micrium-Xilinx-uCOS-II-ML403

Description: microblaze下ucos移植源码，可直接编译运行。-microblaze
Platform: | Size: 161792 | Author: pp | Hits:

[VHDL-FPGA-Verilog] ADC0832_test

Description: ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.-ADC0832 is an 8-bit conversion of the ADC chip, the working frequency of 250Khz, the maximum frequency of up to 400Khz, into two channels, the input voltage can be divided into single-ended or differential form. This test used the form of single-ended voltage input, from the previous years of the CH0 input voltage, the use of Xilinx XC3S200AN development board, Xilinx ise tools and use of ChipScope tool to see into the post-DO data is correct. Validated, input voltage range is 0V- 5.5V, when the voltage reaches 5.5V, the full-scale.
Platform: | Size: 3628032 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] XilinxISE8

Description: This tutorial gives a description of the features and additions to Xilinx® ISE™ 8.2i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”-This tutorial gives a description of the features and additions to Xilinx® ISE™ 8.2i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”
Platform: | Size: 1563648 | Author: JERRY | Hits:

[VHDL-FPGA-Verilog] clock_divider_lab

Description: Clock divider lab uusing xilinx tools, and simulator like modelsim
Platform: | Size: 2048 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[Program doc] EmbeddedSystemToolsReferenceGuide

Description: Xilinx嵌入式工具参考手册，包括XPS，SDK等功能说明-Embedded System Tools Reference Guide
Platform: | Size: 1498112 | Author: 庞士元 | Hits:

[Other] FPGA_Tutorial

Description: This document serves as an example based tutorial to programming the Spartan 3 FPGA included in your parts kit using Xilinx ISE Tools. A Basic working knowledge of how to create schematics in Xilinx is required. The Spartan 3 FPGA can be programming directly from the Xilinx ISE package, greatly simplifying and expediting the design process. Programming the FPGA using a schematic, state diagram, or verilog module is a universally simple and straightforward process.
Platform: | Size: 253952 | Author: Mohamed Saleh | Hits:

[Other] demodulateur_FM2

Description: FM demodulator with dsp tools xilinx system generetor for dsp.
Platform: | Size: 19456 | Author: elhaouari44 | Hits:

[VHDL-FPGA-Verilog] lab_instructions1

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1188864 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] lab_instructions2

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 2244608 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] lab_instructions3

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1048576 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] Spartan-3ADSPs

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1040384 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.
Platform: | Size: 56320 | Author: zzy | Hits:
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