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[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 Xilinx提供

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Platform: | Size: 889856 | Author: 司法 | Hits:

[VHDL-FPGA-Verilog] simple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] task_function

Description: 自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过-I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through
Platform: | Size: 235520 | Author: lg | Hits:

[VHDL-FPGA-Verilog] xilinx_iic_spi

Description: xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
Platform: | Size: 1765376 | Author: 杨子树 | Hits:

[VHDL-FPGA-Verilog] I2CController

Description: Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx
Platform: | Size: 22528 | Author: iversn | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: | Size: 70656 | Author: JUPP | Hits:

[VHDL-FPGA-Verilog] IPcore_fifo_testbench

Description: 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
Platform: | Size: 1024 | Author: 张学锋 | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Demux modules and test simulations with various combinations of input and output vectors.I am new to Verilog.I am learning it through a electronic system design course on my college.I am interested in downloading a single .zip file from this site,Verilog code for MAC data layer protocol.I hope you will consider my request.
Platform: | Size: 5120 | Author: Igor | Hits:

[VHDL-FPGA-Verilog] 32_bit_mpu

Description: I got my semester project on IMPLEMENTATION OF 32 BIT MIPS processor and implementation on XILINX spartan 3e.i made thys code on verilog and includes LCD interfacing with the kit
Platform: | Size: 2109440 | Author: TUSHAR ANAND | Hits:

[VHDL-FPGA-Verilog] verilog-hdl

Description: 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full description ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
Platform: | Size: 6459392 | Author: 龙 斌 | Hits:

[Software Engineering] ME-Project-Reference

Description: This project used code verilog to load on Kit Xilinx Spartan 3A. Wireless Sensor Nodes Processor Architecture and Design.I prefered on the internet
Platform: | Size: 197632 | Author: thuanbk | Hits:

[VHDL-FPGA-Verilog] drv_dm900

Description: 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
Platform: | Size: 7168 | Author: wtn | Hits:

[VHDL-FPGA-Verilog] udpip

Description: 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.
Platform: | Size: 7168 | Author: 汪洋 | Hits:

[matlab] 源码 基于XILINX FPGA的ofdm通信系统基带设计

Description: verilog 源码 基于XILINX FPGA的ofdm通信系统基带设计(Experiment of digital signal processing: parallel filtering experiment code. I hope it will help.)
Platform: | Size: 3769344 | Author: Oliver-H | Hits:

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