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[Other resource] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767014 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] music

Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Platform: | Size: 8192 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] pci32_top_pci32_v4_8.vhd

Description: XINLINX的PCI核源文件代码,这是我在网上找的，希望对大家有用！-THE SOURCE FILE OF PCI CORE，IT IS FOUND ON INTERNET. MAYBE IT IS USEFUL.
Platform: | Size: 5120 | Author: qiuli | Hits:

[VHDL-FPGA-Verilog] Xilinx_yuanyu

Description: 本文详细介绍了xinlinx公司fpga的原语使用方法，原语相对于调用核来说更简单明了，推荐初学者多使用原语-This paper describes the xinlinx' s fpga use the original language, the original language as opposed to call-core is more simple and straightforward, it is recommended for beginners to use more of the original language
Platform: | Size: 594944 | Author: kaishi | Hits:

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