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- 【VHDL-FPGA-Verilog】基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
Update : 2025-09-03 | Size : 19784704