[VHDL-FPGA-Verilog] S03_基于ZYNQ的DMA与VDMA的应用开发

Description: vivado DMA&VDMA example text of zynq
Platform: | Size: 9689088 | Author: kernelstory | Hits:

[VHDL-FPGA-Verilog] S04_基于ZYNQ的HLS 图像算法设计基础

Description: vivado image processing example text of zynq
Platform: | Size: 7998464 | Author: kernelstory | Hits:

[VHDL-FPGA-Verilog] S05_example_Network

Description: vivado lwip example text of zynq
Platform: | Size: 3401728 | Author: kernelstory | Hits:

[VHDL-FPGA-Verilog] sram

Description: Read and write SRAM memory block and Verilog code in FPGA
Platform: | Size: 1379328 | Author: bin_mm3 | Hits:

[VHDL-FPGA-Verilog] verilog实现dds

Description: The function of signal generator is realized based on FPGA, which is a good reference.
Platform: | Size: 2594816 | Author: sudochang | Hits:

[VHDL-FPGA-Verilog] Rs通用编码

Description: 适用各种体制的RS编码，Verilog实现，配置本原多项式参数即可
Platform: | Size: 1748 | Author: 1314@someone | Hits:

[VHDL-FPGA-Verilog] nexys3--ucf

Description: nexys3--ucf is the ucf file for nexys3 board
Platform: | Size: 4174 | Author: jcljob | Hits:

[VHDL-FPGA-Verilog] 运动目标检测

Description: shi xian yun dong jian ce .
Platform: | Size: 13312 | Author: zero_lz | Hits:

[VHDL-FPGA-Verilog] AHB-task-slave-master

Description: AHB master behavior level model, AHB slave model
Platform: | Size: 2048 | Author: 鱼在在藻 | Hits:

[VHDL-FPGA-Verilog] Weighted-Round-Robin-Arbiter-master

Description: Verilog implementation of priority rotation algorithm with weight
Platform: | Size: 437248 | Author: 鱼在在藻 | Hits:

[VHDL-FPGA-Verilog] module_average_filter

Description: Verilog implementation of a median filtering algorithm
Platform: | Size: 4096 | Author: 兴鹏 | Hits:

[VHDL-FPGA-Verilog] camera_ov7725_sample

Description: Realize the camera ov7725 acquisition of video, output through VGA port. Fpga model EGO1, you can modify the XDC file.
Platform: | Size: 15090688 | Author: beTTer_every | Hits: