Embeded-SCM Develop List Page 617

[VHDL-FPGA-Verilog] shuzizhong

Description: (1) 24 hour time display (time, minute, second); (2) have time setting function (time and minute); (3) it has the function of whole point. (4) realize the alarm clock function (timing, noise);
Platform: | Size: 4346880 | Author: Goddd | Hits:

[DSP program] Code2407_cc2000

Description: Programme of 2407 DSP
Platform: | Size: 670720 | Author: 大哥我说的 | Hits:

[Embeded-SCM Develop] （02）STM32例程(STM32F103C8T6)

Description: STM32 OLED display driver complete routine
Platform: | Size: 336896 | Author: hujunyi5188 | Hits:

[Embeded-SCM Develop] 龙邱K60F系列核心板九轴例程

Description: The implementation of the nine axis sensor is realized. Processing of single chip computer program
Platform: | Size: 7007232 | Author: asdasdasd231 | Hits:

[VHDL-FPGA-Verilog] 1

Description: Simple combinatorial logic design, design of simple frequency division sequential logic circuit and Realization of counting frequency division timing circuit by conditional statement
Platform: | Size: 1024 | Author: 随风sf | Hits:

[VHDL-FPGA-Verilog] 新建文本文档 (3)

Description: Using a function in Verilog, a complex combinational logic circuit is realized with a always block, and the difference between blocking assignment and non blocking assignment
Platform: | Size: 1024 | Author: 随风sf | Hits:

[SCM] eda

Description: In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM
Platform: | Size: 3072 | Author: 随风sf | Hits:

[Embeded-SCM Develop] 根文件系统的制作leeyan

Description: The basic structure of the root file system is introduced in detail, as well as the system library, kernel module and application program needed to be selected. Various initialization script files are configured, and the
Platform: | Size: 473088 | Author: Y_Lee | Hits:

[SCM] 74ALS

Description: this is 74ALS dwonload it
Platform: | Size: 24576 | Author: Pallav | Hits: