[Embeded-SCM Develop] 电表 645 详细实现 代码 源码

Description: 电表 645 的详细实现，可以参考,具有参考价值
Platform: | Size: 20567369 | Author: haifengyt | Hits:

[SCM] STM8S_modbus

Description: freemodbus slave port to stm8s103
Platform: | Size: 11097088 | Author: abcdfly | Hits:

[SCM] embedded

Description: A water heater system based on STM32. This system uses stm32f103vet6 core board, temperature sensor DS18B20, LCD 12864, DC motor module, independent button module, and buzzer module. In addition to temperature detection,
Platform: | Size: 3025920 | Author: ling_zed | Hits:

[Embeded-SCM Develop] LoRa通用库

Description: Stm32l151 Lora general library
Platform: | Size: 23550976 | Author: txh123 | Hits:

[SCM] 51黑论坛_数码管显示程序

Description: Proteus + stm32 + tm1637 display simulation, simulation digital tube when the refresh rate is too low, a digital one, according to which an improvement.
Platform: | Size: 376832 | Author: xiaoAY. | Hits:

[DSP program] XMC4400_Digital_CCM_PFC_v1_0_0

Description: Digital PFC control demo code
Platform: | Size: 17037312 | Author: younglong | Hits:

[Embeded-SCM Develop] c8t62812liushui

Description: Stm32f103c8t6 flow lamp project of 2812
Platform: | Size: 4136960 | Author: ..........枫 | Hits:

[SCM] 智能家居

Description: This design is a smart home which uses STM32 as the main controller and esp8266 WiFi module for data transmission to detect the warehouse environment. This smart home detects the warehouse environment in real time throug
Platform: | Size: 3821568 | Author: wgq1020 | Hits:

[ARM-PowerPC-ColdFire-MIPS] 贪吃蛇游戏最终版

Description: snack stm32f103zet6 4.3
Platform: | Size: 6123520 | Author: 杜小娇 | Hits:

[ARM-PowerPC-ColdFire-MIPS] FreeRTOS 10.0.1实现互斥信号量

Description: 基于STM32F103 + FreeRTOS v10.0.1实现互斥信号量
Platform: | Size: 3462907 | Author: yinghuajf_0215@sohu.com | Hits:

[VHDL-FPGA-Verilog] 4乘4键盘扫描控制器

Description: 1. The key value is encoded in hexadecimal, i.e. 16 keys display hexadecimal numbers respectively 0 ~ F, the corresponding relationship of keys is as follows: the top line is 0 ~ 3 from left to right, The second row is 4
Platform: | Size: 3444736 | Author: Minbadly | Hits:

[VHDL-FPGA-Verilog] 0-999随机数

Description: 1. Design and implement a random number generating circuit, which generates randomly every 2 seconds Form a number between 0 and 999 and display it on the nixie tube Generated random number. 2. Set a reset key for the sy
Platform: | Size: 4747264 | Author: Minbadly | Hits: