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This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
Update : 2025-02-04 Size : 2kb Publisher : serg_86

This module does Complex MAC based on Altera Stratix 2 DSP Blocks.
Update : 2025-02-04 Size : 85kb Publisher : serg_86

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FPGA Up/Down couner Module
Update : 2025-02-04 Size : 439kb Publisher : serg_86

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This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
Update : 2025-02-04 Size : 1.93mb Publisher : serg_86

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This module converts 8 bit SDR flow to 4 bit DDR RGMII flow, proved on Altera Cyclone 3 devices.
Update : 2025-02-04 Size : 1.95mb Publisher : serg_86

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This module does Complex multiplication based on Xilinx DSP48E1 dsp block. Proved on xilinx Virtex 6 Devices
Update : 2025-02-04 Size : 649kb Publisher : serg_86

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This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.
Update : 2025-02-04 Size : 15.33mb Publisher : 剑姬2

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Modular pipelined flicker
Update : 2025-02-04 Size : 93kb Publisher : 大大大大帅哥

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terminal for CPU test
Update : 2025-02-04 Size : 10.2mb Publisher : Andyyjx

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The method of learning to use the firmware library function to write the flow lamp and key
Update : 2025-02-04 Size : 21.17mb Publisher : 大熊猫panda11

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c language help study
Update : 2025-02-04 Size : 26kb Publisher : 玩服打

Three algorithms of attitude calculation for mpu6050 based on STM32 code source
Update : 2025-02-04 Size : 10.3mb Publisher : 黑耀辉
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