Embeded-SCM Develop List Page 972

Embeded-SCM Develop list

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1602显示 Downloaded：0: 51 singlechip LCD display program, including source code, initialization code, low level hardware driver code and so on.
Update : 2025-02-07 Size : 26kb Publisher : yangbin2566
NRF24L01一对一接收模块 Downloaded：0: 2.4G transceiver based on 51 single chip microcomputer, which contains engineering documents.
Update : 2025-02-07 Size : 53kb Publisher : yangbin2566
led Downloaded：0: Two LED using STM32 to achieve marquee program
Update : 2025-02-07 Size : 1.85mb Publisher : Samanthamao
PWM Downloaded：0: The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustment step 0.1%.
Update : 2025-02-07 Size : 61kb Publisher : jcg17
pci9504 Downloaded：0: The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus
Update : 2025-02-07 Size : 20kb Publisher : jcg17
stm32 Downloaded：0: Communication between STM32 and FPGA Implementation in the way of SPI
Update : 2025-02-07 Size : 1.39mb Publisher : 王晓飞
stm32 Downloaded：0: The communication with ADF4351 is realized by using SPI in the way of STM32F103, and the control of the PLL chip is realized
Update : 2025-02-07 Size : 2.92mb Publisher : 王晓飞
stm32 Downloaded：0: The implementation of the STM32 seat FFT function, do not need FPGA, only STM32 can be implemented
Update : 2025-02-07 Size : 4.59mb Publisher : 王晓飞
stm32 Downloaded：0: STM32F103 realizes low frequency arbitrary waveform generator, and realizes the function of waveform generation.
Update : 2025-02-07 Size : 3.99mb Publisher : 王晓飞
stm32 Downloaded：0: STM32F103 realizes the function of controlling the DDS module and uses the SPI communication mode
Update : 2025-02-07 Size : 2.62mb Publisher : 王晓飞
vga_7_0728 Downloaded：0: With vga digital clock, through the serial port can control the time display
Update : 2025-02-07 Size : 12.32mb Publisher : wuyezhiyue
display_1 Downloaded：0: Verilog program can be completed on the digital clock fpga procedures
Update : 2025-02-07 Size : 600kb Publisher : wuyezhiyue

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