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VHDL-FPGA-Verilog list
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IL SAGIT D'UN FIFO EN DESCRIPTION DE LANGUAGE vhdl
Update : 2025-02-26 Size : 1kb Publisher : alaala

classical tutorial for DE2 development.
Update : 2025-02-26 Size : 28.83mb Publisher : 六味地黄丸

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The data includes the function of receiving data from the NRF24l01 wireless chip implemented by Verilog and implemented on the EP4CE22F17 chip.
Update : 2025-02-26 Size : 20kb Publisher : 杨雷

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This information includes UART communication program written by FPGA (EP4CE22F17 model), and most importantly, it contains serial port baud rate tunable, including some common baud rate.
Update : 2025-02-26 Size : 3.2mb Publisher : 杨雷

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This module calculates ethernet crc32 on fpga using table method
Update : 2025-02-26 Size : 1kb Publisher : serg_86

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Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado
Update : 2025-02-26 Size : 768kb Publisher : Alva007

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Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado
Update : 2025-02-26 Size : 231kb Publisher : Alva007

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This module does Accumulate operation used in dsp. Tested on fpga.
Update : 2025-02-26 Size : 1kb Publisher : serg_86

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This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
Update : 2025-02-26 Size : 2kb Publisher : serg_86

This module does Complex MAC based on Altera Stratix 2 DSP Blocks.
Update : 2025-02-26 Size : 85kb Publisher : serg_86

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FPGA Up/Down couner Module
Update : 2025-02-26 Size : 439kb Publisher : serg_86

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This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
Update : 2025-02-26 Size : 1.93mb Publisher : serg_86
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