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VHDL-FPGA-Verilog list
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SMG
Downloaded:1
The realization of dynamic scanning BCD code displayed on the digital tube --verilog
Update
: 2025-01-09
Size
: 3kb
Publisher
:
Yukioooo
AD9854programme
Downloaded:0
FPGA is used to start AD9854 for frequency sweep, and is used for frequency characteristic tester. And send data through the Wify module
Update
: 2025-01-09
Size
: 12.32mb
Publisher
:
Chenweiyu14
sfifo
Downloaded:0
A fifo controller verilog description.
Update
: 2025-01-09
Size
: 1kb
Publisher
:
123yyy
IICPractice
Downloaded:0
The program of sending and receiving IIC bus on FPGA
Update
: 2025-01-09
Size
: 3.29mb
Publisher
:
giraffe1234
project2
Downloaded:0
Verilog based on the quartus platform to build a serial communication model, suitable for beginners.
Update
: 2025-01-09
Size
: 114kb
Publisher
:
锂离子
shiftreg44
Downloaded:0
Base counter and shift register for a cache primitive
Update
: 2025-01-09
Size
: 5kb
Publisher
:
aasdd
src
Downloaded:0
Spartan-3E. Working VHDL code for amplifier LTC6912, adc LTC1407A-1, dac LTC2624. Archive includes vhdl files and ucf file with comments. Create new project add files and it will be to work.
Update
: 2025-01-09
Size
: 8kb
Publisher
:
evjen20
FiniteStateMachine
Downloaded:0
A finite state machine designed for identifying expression patterns
Update
: 2025-01-09
Size
: 137kb
Publisher
:
BXYMartin
n-bit adder
Downloaded:0
n-bit optimized adder using VHDL
Update
: 2025-01-09
Size
: 1kb
Publisher
:
mohAdel9
1602 clock
Downloaded:0
Simple display time function - minute seconds and text
Update
: 2025-01-09
Size
: 8.94mb
Publisher
:
楚生
Linux_rev3.1
Downloaded:0
Altera FPGA PCIe driver, used in the actual project
Update
: 2025-01-09
Size
: 269kb
Publisher
:
qiangang
ethernet_loopback
Downloaded:0
Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP sta
Update
: 2025-01-09
Size
: 22.83mb
Publisher
:
marktuwen
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