VHDL-FPGA-Verilog List Page 195

VHDL-FPGA-Verilog list

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i2c Downloaded：0: I2C logic implementation, complete I2C logic function, can realize the function of I2C main equipment
Update : 2025-01-11 Size : 8.93mb Publisher : 内蒙古浪子
sw_debounce Downloaded：0: Key edge dithering program with pulse edge detection method
Update : 2025-01-11 Size : 4.22mb Publisher : 水白三千
soble Downloaded：0: Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.
Update : 2025-01-11 Size : 5.6mb Publisher : 我是陌陌同学
Abel4w Downloaded：0: programming language using
Update : 2025-01-11 Size : 1.16mb Publisher : sdsui28
vctqf Downloaded：0: Course designed to prepare the matlab program code, MIT Artificial Intelligence Laboratory identification of the target source, Nonlinear discrete system identification.
Update : 2025-01-11 Size : 7kb Publisher : tyasiu
btebv Downloaded：0: Using MATLAB dynamic clustering or iterative self-organizing data analysis, Sampling from a priori probability, calculate the weight, Gaussian white noise generator.
Update : 2025-01-11 Size : 7kb Publisher : tyasiu
nfqud Downloaded：0: Using MATLAB dynamic clustering or iterative self-organizing data analysis, The performance of the program has reached a high level, MinkowskiMethod algorithm.
Update : 2025-01-11 Size : 7kb Publisher : tyasiu
byaxj Downloaded：0: The IMC - PID is using the internal model control principle for PID parameters is calculated, Achieve a grayscale image and further control for video surveillance, Can be widely used in data analysis and forecast data.
Update : 2025-01-11 Size : 7kb Publisher : yiufouhen
i2c_40g_pos Downloaded：0: always @ ( posedge clk_100m or posedge rst_100m) begin if( rst_100m == 1'b1 ) begin SCKcnt <= 10'd0; end else if( SCKen == 1'b1 ) begin if(SCKcnt != I2CSCK_DIV) begin SCKcnt <= SCKcnt + 1'b1; end else begin SCKcnt <= 10'
Update : 2025-01-11 Size : 3kb Publisher : CHENLU0707
MiS603 FPGA开发教程V1.4(HDL) Downloaded：0: MIZ MIS603 data, FPGA, VERLOG language, introduced some of the interface driver design
Update : 2025-01-11 Size : 17.46mb Publisher : huhotto
liushui Downloaded：0: FPGA flow lamp program to realize variable speed and reverse rotation function
Update : 2025-01-11 Size : 356kb Publisher : 马特王尔菲
Johnaon_counter Downloaded：0: This design is a six-bit Johnson counter, first of all to introduce what is the Johnson counter, it also called the torsion ring counter, is a kind of n-bit trigger to represent the 2n state of the counter. It differs fr
Update : 2025-01-11 Size : 6kb Publisher : Leegege

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