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VHDL-FPGA-Verilog list
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axi_lite_user
Downloaded:0
Axi_lite_user official sample, streamline function, apply to zynq series Axi bus
Update
: 2025-01-12
Size
: 4.42mb
Publisher
:
haixng
RGBtoYUV
Downloaded:0
Transform RGB data of a bmp to YUV.
Update
: 2025-01-12
Size
: 36kb
Publisher
:
wonderful
VHDL实用教程_潘松_王国栋
Downloaded:0
This is a good tutorial for learning VHDL language. Very suitable for beginners to learn
Update
: 2025-01-12
Size
: 2.79mb
Publisher
:
从小就够炫
串口通信
Downloaded:0
The program mainly to achieve FPGA serial communication, including source code and serial debugging tools
Update
: 2025-01-12
Size
: 768kb
Publisher
:
youngck
SPI_master
Downloaded:0
simple program for SPI-Master
Update
: 2025-01-12
Size
: 1kb
Publisher
:
jxls378816
FPGA TFT 驱动
Downloaded:0
FPGA code for driving TFT.
Update
: 2025-01-12
Size
: 530kb
Publisher
:
虞yuyuyuyuyu
spi
Downloaded:0
SPI principle and its implemetation in verilog HDL
Update
: 2025-01-12
Size
: 24kb
Publisher
:
gentlegirl5
AD9512_coe
Downloaded:0
AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Update
: 2025-01-12
Size
: 1kb
Publisher
:
小黄a小黄蛋
AD9512_ISE
Downloaded:0
AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Update
: 2025-01-12
Size
: 4.83mb
Publisher
:
小黄a小黄蛋
lab2
Downloaded:0
Verilog lab2 is used for learning vivado
Update
: 2025-01-12
Size
: 8kb
Publisher
:
Chappa
lab4
Downloaded:0
Verilog lab4 is used for learning vivado
Update
: 2025-01-12
Size
: 37kb
Publisher
:
Chappa
lab5
Downloaded:0
Verilog lab5 is used for learning vivado
Update
: 2025-01-12
Size
: 7kb
Publisher
:
Chappa
«
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.19
.20
.21
.22
.23
224
.25
.26
.27
.28
.29
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4311
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