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VHDL-FPGA-Verilog list
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verilog_PLL
Downloaded:0
All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simulation.
Update
: 2025-01-12
Size
: 11kb
Publisher
:
小米1
Zet-1.3.1
Downloaded:0
ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 interface .
Update
: 2025-01-12
Size
: 2.37mb
Publisher
:
VectorIII
sp6
Downloaded:0
Using, a company developed by FPGA, is a LED running water lamp program.
Update
: 2025-01-12
Size
: 109kb
Publisher
:
xshtx
vga_top2
Downloaded:0
EDA class set in the VGA display, containing the source code and the entire project various documents
Update
: 2025-01-12
Size
: 9.42mb
Publisher
:
migamigamiga
FIFO_ASY
Downloaded:0
Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.
Update
: 2025-01-12
Size
: 2kb
Publisher
:
253765952
按键控制led
Downloaded:0
Press button to control the LED lights on and off
Update
: 2025-01-12
Size
: 4.95mb
Publisher
:
baby321
fir
Downloaded:0
Power filter is composed of capacitance and inductance and resistance of filter circuit.Specific frequency of the filter to the power cord or the point that the frequency of frequency effectively filter out, get a specif
Update
: 2025-01-12
Size
: 7kb
Publisher
:
6Andd7
序列检测器
Downloaded:0
This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010
Update
: 2025-01-12
Size
: 18kb
Publisher
:
不唯花开
code.sources
Downloaded:0
zcscscsasfsdfsfasfasf
Update
: 2025-01-12
Size
: 3kb
Publisher
:
辕门暮雪
RS_422
Downloaded:0
On the K7FPGA, using Verilog language RS422 serial port, because did not find Verilog, so chose VHDL
Update
: 2025-01-12
Size
: 5.61mb
Publisher
:
allen3zsy
Verilog HDL(第4版)[王金明][电子教案]
Downloaded:0
Verilog HDL (Fourth Edition) [] [Wang Jinming].rar e-lesson plans note ppt plans.
Update
: 2025-01-12
Size
: 5.18mb
Publisher
:
lart
src
Downloaded:0
user FPGA and DAC generate DDS
Update
: 2025-01-12
Size
: 29kb
Publisher
:
WOO8
«
1
2
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.34
.35
.36
.37
.38
239
.40
.41
.42
.43
.44
...
4311
»
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