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VHDL-FPGA-Verilog list
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The frequency division of the clock signal in the FPGA is used as the reference frequency, the other frequency is used as input, and the input frequency is displayed in the digital tube.
Update : 2025-01-12 Size : 8.04mb Publisher : 狄克推多

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Implementation of IIC protocol in Verilog language
Update : 2025-01-12 Size : 1kb Publisher : 小黑93

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count from 0 to 9,and the lum become more and more high
Update : 2025-01-12 Size : 1.29mb Publisher : Eris

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my English very bad,so I don't write
Update : 2025-01-12 Size : 27kb Publisher : 山雨林

systemverilog verification methodology
Update : 2025-01-12 Size : 43.68mb Publisher : 影魅

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arithmetic and logic unit
Update : 2025-01-12 Size : 1kb Publisher : 请问让人讨厌

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FPGA serial communication, in the realization of character data transmission, and STM32 serial communication similar
Update : 2025-01-12 Size : 3.2mb Publisher : helmess

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4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction
Update : 2025-01-12 Size : 1kb Publisher : 柳弦

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Seven segment digital decoder, 0~9 can display a total of 10 characters.
Update : 2025-01-12 Size : 432kb Publisher : Stella\

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Clock, with alarm set, the whole point timekeeping function, alarm clock with stop button
Update : 2025-01-12 Size : 716kb Publisher : nexr

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vga is in the platform of fpga
Update : 2025-01-12 Size : 1kb Publisher : TonyTom

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Many versions of the original download were not available. This version is available
Update : 2025-01-12 Size : 760kb Publisher : liuyijian
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