VHDL-FPGA-Verilog List Page 3176

VHDL-FPGA-Verilog list

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hdbn_latest.tar Downloaded：0: This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-
Update : 2025-04-22 Size : 195kb Publisher : chaitanya
bluespec-80211atransmitter_latest.tar Downloaded：0: This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.
Update : 2025-04-22 Size : 259kb Publisher : chaitanya
turbo Downloaded：0: Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
Update : 2025-04-22 Size : 150kb Publisher : 秋晨
jiyuchuankoujishu Downloaded：0: BASIC IN HDL language,chuankou jishu
Update : 2025-04-22 Size : 301kb Publisher : tongchao
GAFF Downloaded：0: Galois field GF (q) multiplier design, the complete source code.
Update : 2025-04-22 Size : 2kb Publisher : dayu1994
sumador Downloaded：0: sumer vhdl code for FPGA of Xilinx
Update : 2025-04-22 Size : 1kb Publisher : Lowis
manch Downloaded：1: The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design documents and simulation test file. In the Modelsim simul
Update : 2025-04-22 Size : 120kb Publisher : dayu1994
CORDIC_SINE Downloaded：0: xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
Update : 2025-04-22 Size : 13.78mb Publisher : 刘伟
chuzucheVHDL Downloaded：0: Taximeter written with VHDL program, has a detailed description of
Update : 2025-04-22 Size : 1kb Publisher : 刘伟
dig_pll Downloaded：0: A simple digital PLL can generate an input in phase with the same frequency output clock
Update : 2025-04-22 Size : 21kb Publisher : 刘伟
CPU11111 Downloaded：0: altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
Update : 2025-04-22 Size : 1kb Publisher : 张寒枫
uart Downloaded：0: verilog RS232
Update : 2025-04-22 Size : 78kb Publisher : cuiqiang

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