VHDL-FPGA-Verilog List Page 3204

VHDL-FPGA-Verilog list

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traffic Downloaded：0: Light traffic by xilinx
Update : 2025-04-21 Size : 401kb Publisher : mohab
BCD_sevenseg Downloaded：0: BCD seven segment by xilinx
Update : 2025-04-21 Size : 154kb Publisher : mohab
TLC5510 Downloaded：0: VHDL implementation of the TLC5510 control, with signaltap simulation diagram
Update : 2025-04-21 Size : 2.93mb Publisher : 成天
flipflop Downloaded：0: FlipFlop VDHL by xilinx
Update : 2025-04-21 Size : 268kb Publisher : mohab
latch Downloaded：0: Latch VDHL by xilinx
Update : 2025-04-21 Size : 262kb Publisher : mohab
counter Downloaded：0: Ring Counter implemented in VHDL usign finite state machine design.
Update : 2025-04-21 Size : 1kb Publisher : slash
ADC124 Downloaded：0: Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
Update : 2025-04-21 Size : 1kb Publisher : chenwl
dac121 Downloaded：0: Verilog prepared using high-speed string-type DA-chip dac121 driver code, occupation le small, high efficiency, the current I applied to more products
Update : 2025-04-21 Size : 336kb Publisher : chenwl
ds18b20 Downloaded：1: Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
Update : 2025-04-21 Size : 433kb Publisher : chenwl
ds18b20s4 Downloaded：0: Four DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, enter the address change in accordance with the direct output. Occupy 600 LE resources, as opposed to one-way process, a more streaml
Update : 2025-04-21 Size : 433kb Publisher : chenwl
ds18b20s16 Downloaded：0: 16 DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 1100 LE resources. Suitable for multi-channel probe with the same time, require a shorter acquisition cycle progr
Update : 2025-04-21 Size : 433kb Publisher : chenwl
tlc2543AND11channel Downloaded：0: 11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
Update : 2025-04-21 Size : 32kb Publisher : chenwl

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