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VHDL-FPGA-Verilog list
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CPU
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CPU
Update : 2025-04-21 Size : 2.46mb Publisher : 姚琪儿
polyphase
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The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
Update : 2025-04-21 Size : 267kb Publisher : vadik
AD6635
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The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
Update : 2025-04-21 Size : 497kb Publisher : vadik
ip_digifrec
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The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
Update : 2025-04-21 Size : 67kb Publisher : vadik
prog_dds
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FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
Update : 2025-04-21 Size : 1.18mb Publisher : 张鹏
s
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The choice of VHDL-based computing device, you can choose by selecting the side addition and subtraction with or four kinds of operations, the results of one per clock cycle refresh. Note has been given.
Update : 2025-04-21 Size : 1kb Publisher : cckaa
seven
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VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
Update : 2025-04-21 Size : 1kb Publisher : cckaa
MUX
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source s file of multiplexor
Update : 2025-04-21 Size : 158kb Publisher : trerepaxa
serialports2
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Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
Update : 2025-04-21 Size : 804kb Publisher : yaota
8b10bverilog
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verilog 8b10b
Update : 2025-04-21 Size : 5kb Publisher : ckj
PROCEDURETOWORKINISE
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Procedure to Work in VHDL... by Ashok Kumar . A . M Zebros India
Update : 2025-04-21 Size : 3.33mb Publisher : Ashok
BASICVHDLCODES
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BASIC VHDL DOCUMENTS BY ASHOK KUMAR.A.M ZEBROS INDIA
Update : 2025-04-21 Size : 9kb Publisher : Ashok
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