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VHDL-FPGA-Verilog list
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ModifyInstruction
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Digital loop filter is composed of variable-mode reversible counter. The counter is designed to a 17-bit programmable (variable modulus) reversible counter, counting range is set by an external control of the number of D
Update : 2025-03-20 Size : 1kb Publisher : xxx
VHDLDPLL
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VHDL-based all-digital phase-locked loop design, which contains the core procedures.
Update : 2025-03-20 Size : 164kb Publisher : xxx
2
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Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
Update : 2025-03-20 Size : 155kb Publisher : xxx
h
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VHDL hardware programming language used to achieve two decimal numbers 4 operation, the VHDL language, learning and further understanding.
Update : 2025-03-20 Size : 6kb Publisher : cherry
cpusample
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CPU emulation program written in VHDL. CPU emulation can be carried out, addition multiplication and so on. Which contains the relevant courseware.
Update : 2025-03-20 Size : 5.42mb Publisher : lyn
1149.4VHDL
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Norm 1149.1 implemented in VHDL language.
Update : 2025-03-20 Size : 233kb Publisher : jose
rombcdto7
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rom implementing bcdtosevenseg
Update : 2025-03-20 Size : 1kb Publisher : Amal
ram255x8
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A Basic ram structure with 256 data handling
Update : 2025-03-20 Size : 1kb Publisher : Amal
ram16x8dualport
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A basic dualport ram
Update : 2025-03-20 Size : 1kb Publisher : Amal
bcd7seg
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A BCD to 7 segment circuit
Update : 2025-03-20 Size : 1kb Publisher : Amal
rom16_1_16
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A basic 16 by 16 ROM memory
Update : 2025-03-20 Size : 1kb Publisher : Amal
NIOS_II_SOPC_Develop
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How to implement an Embedd SOPC development by using NIOS II kernel.
Update : 2025-03-20 Size : 86kb Publisher : 邓文凯
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