VHDL-FPGA-Verilog List Page 3311

VHDL-FPGA-Verilog list

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ALUALUcontrol Downloaded：0: To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Update : 2025-03-20 Size : 1.01mb Publisher : 于伟
Move071221133_32 Downloaded：0: With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation
Update : 2025-03-20 Size : 799kb Publisher : 于伟
VHDL Downloaded：0: Crossover Marquee digital control Model Code
Update : 2025-03-20 Size : 5kb Publisher : wst
IU3 Downloaded：0: The file is the RTL of the Sparc s integer unit.
Update : 2025-03-20 Size : 23kb Publisher : nadir
VERILOG Downloaded：0: A very good Verilog courseware, simple easy to understand for beginners, for everyone to share ~
Update : 2025-03-20 Size : 6.31mb Publisher : 李振
viterbi_for_bch Downloaded：0: Viterbi based trellis decoder for (7,4)- binary BCH code
Update : 2025-03-20 Size : 1kb Publisher : shahifaqeer
RS_decoder Downloaded：0: Reed solomon decoder based on table-lookup method VHDL code
Update : 2025-03-20 Size : 4kb Publisher : shahifaqeer
wtut_edif Downloaded：0: Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Update : 2025-03-20 Size : 20kb Publisher : shad
wtut_sc Downloaded：0: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock
Update : 2025-03-20 Size : 104kb Publisher : shad
wtut_ver Downloaded：0: DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF)
Update : 2025-03-20 Size : 25kb Publisher : shad
wtut_vhd Downloaded：1: When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data
Update : 2025-03-20 Size : 35kb Publisher : shad
DFNL Downloaded：0: On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from eith
Update : 2025-03-20 Size : 3kb Publisher : shad

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