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Cordic Core Specification
Update : 2025-03-19 Size : 229kb Publisher : charanyakannan -
1, can display hours, minutes, seconds, can be set 2. With the whole point of the alarm function 3. Can be 12 hours/24 hours display mode switch.
Update : 2025-03-19 Size : 23kb Publisher : 张金 -
matiry key scan code
Update : 2025-03-19 Size : 1kb Publisher : microeric -
altera' s classical training, new exercises, helpful for the beginner.
Update : 2025-03-19 Size : 48kb Publisher : 吴起 -
VHDL classic design metric VHDL frequency counter
Update : 2025-03-19 Size : 271kb Publisher : 刘思行 -
ps2keyboard interface with VHDL codes and it has useful
Update : 2025-03-19 Size : 1kb Publisher : microeric -
led driver， led scan
Update : 2025-03-19 Size : 1kb Publisher : microeric -
Describe: This is VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six d
Update : 2025-03-19 Size : 90kb Publisher : eric carmen -
VHDL-8051IP-based design and verification of nuclear research is an IP I downloaded from the school through the school paper, I feel quite good
Update : 2025-03-19 Size : 5.01mb Publisher : shintar -
1 led8* 8 of the vhdl procedure superfluous in peacetime are interested in play led to a little help from friends
Update : 2025-03-19 Size : 17kb Publisher : 邓忠飞 -
Based on the vending machine circuit quartusII
Update : 2025-03-19 Size : 13kb Publisher : Jady -
VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Update : 2025-03-19 Size : 11kb Publisher : NULL