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VHDL-FPGA-Verilog list
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myAlteraLib
Downloaded:0
myAlteraLib
Update
: 2025-03-17
Size
: 408kb
Publisher
:
LaoY
MASHENGvirlogTutorial
Downloaded:0
MASHENGvirlogTutorial
Update
: 2025-03-17
Size
: 1.5mb
Publisher
:
LaoY
decorder
Downloaded:0
FPGA-driven LED static display, VHDL source code to achieve
Update
: 2025-03-17
Size
: 5kb
Publisher
:
刘新
waveform-generator-o-VHDL-program
Downloaded:0
Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and ca
Update
: 2025-03-17
Size
: 10kb
Publisher
:
刘新
Taxi-automatic-billing
Downloaded:0
Taxi automated billing system verilog code
Update
: 2025-03-17
Size
: 879kb
Publisher
:
刘新
baseband_verilog
Downloaded:0
verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpol
Update
: 2025-03-17
Size
: 26kb
Publisher
:
刘新
hh
Downloaded:0
AD1674 CONTROL VHDL
Update
: 2025-03-17
Size
: 170kb
Publisher
:
wangyl
fpga
Downloaded:0
ISE I2C UART usb vga
Update
: 2025-03-17
Size
: 1.49mb
Publisher
:
xiong
VHDL_for_clock
Downloaded:0
VHDL-based digital clock design, with a complete code, and have the simulation results.
Update
: 2025-03-17
Size
: 50kb
Publisher
:
zpqmal
B_PON_OLT_VHDL
Downloaded:0
ATM-PON(Passive Optical Network) OLT vdhl proj.file
Update
: 2025-03-17
Size
: 15.39mb
Publisher
:
mr.jeon
B_PON_ONU_VHDL
Downloaded:0
ATM-PON ONU vhdl proj. file good luck
Update
: 2025-03-17
Size
: 6.02mb
Publisher
:
mr.jeon
UART
Downloaded:0
Is to use the ISE implementation UART communication can improve the ability of your FPGA.
Update
: 2025-03-17
Size
: 18kb
Publisher
:
dengfeng
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.83
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.86
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.93
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4311
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