VHDL-FPGA-Verilog List Page 3391

VHDL-FPGA-Verilog list

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IPG Downloaded：0: A project Game designed on a DE270 board. It explains all the project and the specification of the used components.
Update : 2025-03-17 Size : 302kb Publisher : Mouna
DE2_70_LTM_CCD Downloaded：0: A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.
Update : 2025-03-17 Size : 3.67mb Publisher : Mouna
TRDB_DC2_UserGuide_061017 Downloaded：0: A DC2 User guide, shows the pin assignment of the camera DC2 used with the DE270 Board.
Update : 2025-03-17 Size : 2.59mb Publisher : Mouna
SRAM_Controller Downloaded：0: A file showing a SRAM controller with a component that could make some image treatment
Update : 2025-03-17 Size : 3kb Publisher : Mouna
bluespec-h264_latest.tar Downloaded：0: h264 vhdl/verilog implementation on FPGA platform
Update : 2025-03-17 Size : 16.07mb Publisher : ravi
LCD-hello Downloaded：0: VHDL syntax hello world for LCD written in VHDL MAXII evaluation board EPM1270F256C5
Update : 2025-03-17 Size : 1kb Publisher : soroush
cs555 Downloaded：0: This is a work written in VHDL language using state machine control cs5550 for AD conversion code inside that contains the logic analyzer with an analysis of documents. Are highly portable.
Update : 2025-03-17 Size : 21.26mb Publisher : 是傲霜
VHDL_2008_-_Just_the_New_Stuff Downloaded：0: VHDL 2008 The new stuff. A guide reference in VHDL
Update : 2025-03-17 Size : 783kb Publisher : henrydcl
decode_display Downloaded：0: FPGA-based digital control of dynamic drivers, using verilog HDL language.
Update : 2025-03-17 Size : 1kb Publisher : 李哲
ds28ea_src Downloaded：0: xilinx fpga implementation of the control interface temperature sensor ds28ea00
Update : 2025-03-17 Size : 28kb Publisher : 张斌
trunk-hdlc Downloaded：0: - 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern i
Update : 2025-03-17 Size : 184kb Publisher :
07-part05 Downloaded：0: multiplier, VHDL verilog file
Update : 2025-03-17 Size : 545kb Publisher : ch.J.H

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