VHDL-FPGA-Verilog List Page 3438

VHDL-FPGA-Verilog list

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PWMtest Downloaded：0: DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Update : 2025-03-16 Size : 137kb Publisher : panda
sensortest Downloaded：0: Light sensor: LED ambient light will show the size, hands blocking the light sensor, LED display the value of a corresponding decrease.
Update : 2025-03-16 Size : 291kb Publisher : panda
altera_mf Downloaded：0: HD or SD I signals, through the development of the FPGA-Audio procedures.
Update : 2025-03-16 Size : 9kb Publisher : 邢占鹏
example1 Downloaded：0: To achieve the clock signal clk is the frequency function is available through the waveform simulation to evaluate the effects.
Update : 2025-03-16 Size : 29kb Publisher : panda
example2 Downloaded：0: moore state machine processes a total of four conditions, idle idle wait for ready signal ready to enter the state decision or sentence to wait for ready signal ruling the state decision will oe, we set the signal low, b
Update : 2025-03-16 Size : 31kb Publisher : panda
example3 Downloaded：0: To achieve a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit.
Update : 2025-03-16 Size : 32kb Publisher : panda
AudioVMix Downloaded：0: SDI signal through the line of synchronization, the column sync and field sync, and through pairs of rows and columns of pixels counted restrictions to the SDI output of processed data
Update : 2025-03-16 Size : 2kb Publisher : 邢占鹏
example4 Downloaded：0: 8-bit DIP switch 0 to 255 with digital display. DIP switch from 1 to 8 corresponds to a high to low, digital tube display corresponding to 0 to 255 values.
Update : 2025-03-16 Size : 29kb Publisher : panda
example5 Downloaded：0: With 8 keys corresponding to eight figures show that the initial value of 0. By key1 to key8 can display 1 to 8 values.
Update : 2025-03-16 Size : 28kb Publisher : panda
AudioVolCtrl Downloaded：0: Prepared by the FPGA through the procedures, SDI audio signal to control the final output of the voice
Update : 2025-03-16 Size : 1kb Publisher : 邢占鹏
example6 Downloaded：0: Key1 and key2 to control the use of the data increases or decreases can be seen by showing the data changes. key1 is to control the data increases, key2 is to control the data reduction. From 0 to 9 displayed. Which butt
Update : 2025-03-16 Size : 27kb Publisher : panda
example7 Downloaded：0: Analog control a crossroads of traffic lights, lights for row1 lateral junctions and row3 vertical junctions lights for row2 and row4.
Update : 2025-03-16 Size : 27kb Publisher : panda

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