VHDL-FPGA-Verilog List Page 3441

VHDL-FPGA-Verilog list

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uart Downloaded：0: uart
Update : 2025-03-16 Size : 769kb Publisher : dasfsaf
FRE Downloaded：0: vhdl
Update : 2025-03-16 Size : 4.55mb Publisher : dasfsaf
reedsolomon Downloaded：0: reed solomon encoder synthesis and simulation is done using verilog and working fine
Update : 2025-03-16 Size : 1.07mb Publisher : priya
ddsm Downloaded：0: Dds feature using vhdl program to try to achieve a look is not for you!
Update : 2025-03-16 Size : 1kb Publisher : maxmilian
uart Downloaded：1: uart-universal aynchronious reciever and transmitter used to connect the pc and fpga to pass the data
Update : 2025-03-16 Size : 3kb Publisher : priya
Verilog Downloaded：0: altera recommended verilog code style tutorial
Update : 2025-03-16 Size : 1.76mb Publisher : blur
f_adder_4bit Downloaded：0: 4 binary full adder, with schematic input in the form of implementation, compiled in the Quartus II 5.1 adoption.
Update : 2025-03-16 Size : 315kb Publisher : lzj
show_numbers Downloaded：0: In the eight seven-segment digital display tube display 8 Student ID, Student ID to be displayed can be changed within the program.
Update : 2025-03-16 Size : 237kb Publisher : lzj
double_shifter6 Downloaded：0: With a string of set-bit bi-directional shift into/and a 6-bit shift register.
Update : 2025-03-16 Size : 294kb Publisher : lzj
ADC0809 Downloaded：0: ADC0809 Driver by VHDL
Update : 2025-03-16 Size : 397kb Publisher : ziyan
ele_clock Downloaded：0: alarm clock
Update : 2025-03-16 Size : 10kb Publisher : 冯程
ctrller Downloaded：0: This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to call the module
Update : 2025-03-16 Size : 9kb Publisher : kaishi

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