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VHDL-FPGA-Verilog list
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Using the Verilog language to achieve 20 points frequency code, easy to understand, after medolsim simulation, correctly anticipated the output waveform frequency to achieve 20 points.
Update : 2025-03-15 Size : 8kb Publisher : 大安

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Verilog written procedures for finite state machines to achieve the detection of a binary sequence, the finite state machine with 8 states, and can be freely modified, as a test.
Update : 2025-03-15 Size : 7kb Publisher : 大安

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4 x 4 keyboard VHDL description and control. 4 x 4 keyboard is a very common input device. Hope that a friend is applying for help.
Update : 2025-03-15 Size : 1.51mb Publisher : zhang

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Image Enhancement algorithms implemented on FPGA in the literature. Papers are added.
Update : 2025-03-15 Size : 3.07mb Publisher : hazan

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Sram controller with 6 commande ports
Update : 2025-03-15 Size : 2kb Publisher : Charles

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Example of a screen shot module in a FPGA (upload bitmap file by RS232)
Update : 2025-03-15 Size : 2kb Publisher : Charles

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for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
Update : 2025-03-15 Size : 224kb Publisher : 龙珠

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In the FPGA design, when the received data need to extract the clock when the data needs to be synchronized, the article introduced in detail the process of data synchronization processing
Update : 2025-03-15 Size : 64kb Publisher : 龙珠

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Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
Update : 2025-03-15 Size : 3kb Publisher : culun

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verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Update : 2025-03-15 Size : 604kb Publisher : culun

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vhdl butterfly algorithm written procedures for your reference ~ ~ ~ can be used for the realization of fft
Update : 2025-03-15 Size : 3kb Publisher : culun

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Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multi
Update : 2025-03-15 Size : 125kb Publisher : culun
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