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VHDL-FPGA-Verilog list
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32-bit PCI reference design, including the nuclear PCI netlist, design reference
Update : 2025-03-15 Size : 1.46mb Publisher : yexianchun

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Written in VHDL mouse driver. Doc
Update : 2025-03-15 Size : 5kb Publisher : 黄海执

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code for for implementing high speed fifo for apturing data from fpga
Update : 2025-03-15 Size : 2kb Publisher : Vikas

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high speed counter that is designed to work at 150MHz.
Update : 2025-03-15 Size : 23kb Publisher : Vikas

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Reached on the use of VHDL program and the number of 9999 did not cover+ anti-bounce function is a very good and practical programs.
Update : 2025-03-15 Size : 497kb Publisher : 黃嘉偉

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This is an English article, is to use FPGA to realize signal processing
Update : 2025-03-15 Size : 195kb Publisher : 小白

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The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
Update : 2025-03-15 Size : 1.19mb Publisher : bluesky428

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FPGA-based realization of the simple clock, only the basic functions of the clock.
Update : 2025-03-15 Size : 1.97mb Publisher : bluesky428

Learning sopc builder customized component among the most classic examples of the most comprehensive, the absolute value
Update : 2025-03-15 Size : 938kb Publisher : 韩向超

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The lectures are mainly talking about Verilog language, the Southeast University, notes that this language has a basic understanding of.
Update : 2025-03-15 Size : 580kb Publisher : fbin

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series under the cyclone, the consumer cases Buffeting counter the reality of the verilog HDL language source code! !
Update : 2025-03-15 Size : 374kb Publisher : wang

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sdram use verilog HDL used to achieve operation of the sdram! On the timing and language skills required!
Update : 2025-03-15 Size : 68kb Publisher : wang
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