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VHDL-FPGA-Verilog list
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digitalclockvhdl
Downloaded:0
VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
Update
: 2025-03-15
Size
: 8kb
Publisher
:
王丽
jinanVerilogHDL
Downloaded:0
Recommended Guide verilig HDL Huawei classic classic
Update
: 2025-03-15
Size
: 1.53mb
Publisher
:
Sem
VHDL
Downloaded:0
VHDL application of ultra-detailed new Graphic Course Guide
Update
: 2025-03-15
Size
: 2.79mb
Publisher
:
Sem
quartusII
Downloaded:0
quartus II English User Guide for new entry, complete the Chinese version
Update
: 2025-03-15
Size
: 825kb
Publisher
:
Sem
pn_generator
Downloaded:0
FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
Update
: 2025-03-15
Size
: 3kb
Publisher
:
胡佳
MyFilter
Downloaded:0
FPGA realization of digital filters using VHDL language to achieve the direct FIR filter type 1, has a good reference value.
Update
: 2025-03-15
Size
: 2kb
Publisher
:
胡佳
example
Downloaded:0
FPGA a large number of examples for reference only, suitable for novices to learn
Update
: 2025-03-15
Size
: 2.48mb
Publisher
:
Sem
Ctl_LCD
Downloaded:0
FPGA control LCD code, measurement can be used for reference purposes only and for reprint please indicate
Update
: 2025-03-15
Size
: 582kb
Publisher
:
Sem
Verilog
Downloaded:0
Verilog language practice and explain (in Chinese), with answers, a must-see new entry
Update
: 2025-03-15
Size
: 259kb
Publisher
:
Sem
tiaozhi_CPLD
Downloaded:0
Several of the modulation signal communication, based on the VHDL language, the simulation waveform related documents, I hope all of you to help
Update
: 2025-03-15
Size
: 273kb
Publisher
:
李建兵
timing_design_of_fpga
Downloaded:0
Mainly, fpga, cpld design design need to pay attention to the timing of the issue and consider
Update
: 2025-03-15
Size
: 945kb
Publisher
:
沧海一笑
fpga_jpeg
Downloaded:0
Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Update
: 2025-03-15
Size
: 101kb
Publisher
:
沧海一笑
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