VHDL-FPGA-Verilog List Page 3459

VHDL-FPGA-Verilog list

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fenpinqi Downloaded：0: Divider design using VHDL language requirement will be 128 Hz pulses were generated through divider 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz frequency of the eight kinds of signal
Update : 2025-03-15 Size : 1kb Publisher : 高原
dds Downloaded：0: DA convert
Update : 2025-03-15 Size : 1kb Publisher : huruifang
lcd1602 Downloaded：0: lcd1602 the reality of the procedure, you can scan the screen line by line
Update : 2025-03-15 Size : 1kb Publisher : 刘峰
iic Downloaded：0: Cpld single-chip computer and communications cpld prepared using vhdl source code
Update : 2025-03-15 Size : 1kb Publisher : 高原
SPWM Downloaded：0: Cpld developed by spwm waves on the generation of vhdl code
Update : 2025-03-15 Size : 345kb Publisher : 高原
33_COMP Downloaded：0: The real number vhdl comparator, is relatively simple, but practical
Update : 2025-03-15 Size : 1kb Publisher : 高原
I2C_Slave Downloaded：0: I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
Update : 2025-03-15 Size : 583kb Publisher : QinZhujun
mul Downloaded：0: VHDL language with Multiplier （Shift sum method）
Update : 2025-03-15 Size : 27kb Publisher : 齐娜
UART_LCD Downloaded：0: Based on Actel s Fusion Series of FPGA serial UART with FIFO
Update : 2025-03-15 Size : 8kb Publisher : 戚海峰
FSKmodulation Downloaded：0: A VHDL program to realize the FSK modulation of digital signals
Update : 2025-03-15 Size : 1kb Publisher : yuanzongliang
FSKdemodulation Downloaded：0: A VHDL program to realize the FSK demodulation of digital signals
Update : 2025-03-15 Size : 1kb Publisher : yuanzongliang
PSKmodulation Downloaded：0: A VHDL program to realize the PSK modulation of digital signals
Update : 2025-03-15 Size : 1kb Publisher : yuanzongliang

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