VHDL-FPGA-Verilog List Page 3574

VHDL-FPGA-Verilog list

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miniuart.tar Downloaded：0: VHDL description with a simple UART interface
Update : 2025-03-09 Size : 6kb Publisher : elvis
state_machine Downloaded：0: Main Mode pci bus control state machine, the main function is to achieve the main batch mode to read and write functions
Update : 2025-03-09 Size : 6kb Publisher : hjy
EDA Downloaded：0: eda
Update : 2025-03-09 Size : 22kb Publisher : 小慧
DM9000A.VerilogHDL Downloaded：0: VerilogHDL language used to achieve code DM9000A controller is the use of FPGA to do an important part of SOPC
Update : 2025-03-09 Size : 17kb Publisher : 溪溪
VGA.VerilogHDL Downloaded：0: VGA controller to achieve the Verilog code, the video very useful to do, despite the need to download
Update : 2025-03-09 Size : 244kb Publisher : 溪溪
miller Downloaded：0: ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice welcome.
Update : 2025-03-09 Size : 37kb Publisher : kinki
CPU_Address_Decode Downloaded：0: cpu address decode
Update : 2025-03-09 Size : 147kb Publisher : zhusq
CRC Downloaded：0: This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
Update : 2025-03-09 Size : 735kb Publisher : heshuiming
canlender_clock Downloaded：0: the number of calendar verilogHDL to achieve the realization of the DE2
Update : 2025-03-09 Size : 2.73mb Publisher : xuekui
ADC0809 Downloaded：0: ADC0809, a complete functional description of each sampling time 0.5 seconds, and displayed. ADC0809 external chip
Update : 2025-03-09 Size : 81kb Publisher : heshuiming
FPGA Downloaded：0: FPGA下载线自己做(参考资料)FPGA下载线自己做(参考资料)
Update : 2025-03-09 Size : 187kb Publisher : lu
200704252 Downloaded：0: ethernet basic concept, from osi 7 layer to tcp ip, easy to learn network technology in a single step!
Update : 2025-03-09 Size : 925kb Publisher : aichixigua

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