VHDL-FPGA-Verilog List Page 3613

VHDL-FPGA-Verilog list

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music Downloaded：0: FPGA-based music generator designed to EDA technology as the core of the ASIC can be carried out in a programmable system-on-chip integration of the new design method
Update : 2025-02-01 Size : 216kb Publisher : rabbit
VHDL06 Downloaded：0: 16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
Update : 2025-02-01 Size : 1kb Publisher : yanyinhong
vending_machine Downloaded：0: Vending machine model, can set the price and quantity of goods. 0.5 yuan and 1 yuan coin. Can return a maximum of 1.5 per head.
Update : 2025-02-01 Size : 317kb Publisher : lijiang
minimigJ_source_04_08_2008 Downloaded：0: Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
Update : 2025-02-01 Size : 191kb Publisher : lihard
packer Downloaded：0: verilog data packer verilog data packer verilog data packer
Update : 2025-02-01 Size : 3kb Publisher : siuyuen
fpga64_027 Downloaded：0: VHDL source codes of the FPGA64, a fpga implementation of the C64 computer. Version for the c-one fpga board.
Update : 2025-02-01 Size : 184kb Publisher : lihard
T65_v302 Downloaded：0: VHDL source codes of a 65xx compatible cpu core. Version 302.
Update : 2025-02-01 Size : 28kb Publisher : lihard
SubDDS Downloaded：0: generate the sine wave using DSP Builder
Update : 2025-02-01 Size : 7kb Publisher : loo
genode-fx-2009-03 Downloaded：0: Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs.
Update : 2025-02-01 Size : 1.25mb Publisher : lihard
SDRAM_VerilogCode Downloaded：0: FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
Update : 2025-02-01 Size : 26kb Publisher : 姜琰俊
FPGA_DDR_SDRAMverilog Downloaded：0: Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to write and read).
Update : 2025-02-01 Size : 466kb Publisher : 姜琰俊
vhdlCompetition Downloaded：0: vhdl competition
Update : 2025-02-01 Size : 378kb Publisher : 吴小平

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