VHDL-FPGA-Verilog List Page 3625

VHDL-FPGA-Verilog list

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cpu Downloaded：0: CPU design can be made
Update : 2025-02-01 Size : 136kb Publisher : 包小平
HardCamera Downloaded：0: The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the comp
Update : 2025-02-01 Size : 5kb Publisher : Joelmir J Lopes
RS232capture Downloaded：0: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232
Update : 2025-02-01 Size : 39kb Publisher : Joelmir J Lopes
divide Downloaded：0: It is n-bit sequential divider in verilog language
Update : 2025-02-01 Size : 1kb Publisher : Lisha
ram Downloaded：0: ram in the vhdl source code to achieve colloy
Update : 2025-02-01 Size : 1.83mb Publisher : mamou
lab1 Downloaded：0: lab1 report, with codelab1 report, with code
Update : 2025-02-01 Size : 323kb Publisher : rui@rui.com
sopcniosexample Downloaded：0: Sopc through the quartusII to build a simple system nios, nios there is also a simple example of the steps in detail
Update : 2025-02-01 Size : 1.13mb Publisher : maylag_1
seven_segment Downloaded：0: Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
Update : 2025-02-01 Size : 2kb Publisher : Truman, Chien
state_machine_design Downloaded：0: This is a state machine on the information, which Moore and Miller explained the design of state machine instances, and there are examples of very detailed.
Update : 2025-02-01 Size : 471kb Publisher : maylag_1
ad_conv Downloaded：0: CPLD to control the use of AD to voltage sampling, and sampling the value of output
Update : 2025-02-01 Size : 1kb Publisher : 帅
voltage_measure Downloaded：0: The use of CPLD measurement range of the input signal, save value
Update : 2025-02-01 Size : 1kb Publisher : 帅
dig_scan Downloaded：0: The AD sample into the eight-bit decimal numerical size, and dynamic display with digital control
Update : 2025-02-01 Size : 1kb Publisher : 帅

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