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VHDL-FPGA-Verilog list
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CPU-Altera-FPGA
Downloaded:0
EASY TO USE
Update
: 2025-02-01
Size
: 177kb
Publisher
:
zhangfan
canbus
Downloaded:0
the realization of verilog and VHDL code of the can bus interface
Update
: 2025-02-01
Size
: 93kb
Publisher
:
bsyy
Quartus
Downloaded:0
1. Seven-Segment LED Decoder 2.4 M 3.4 people voting machine counters ~ with addition and subtraction and by-bit binary function
Update
: 2025-02-01
Size
: 1kb
Publisher
:
胡志伟
floating-point-adder1
Downloaded:0
floating point adder based on VHDL
Update
: 2025-02-01
Size
: 9kb
Publisher
:
Rosen
Quartus32
Downloaded:0
Counter 2 decimal 1.8421 yards. Sub-frequency coefficient of 8, duty cycle of the divider 3 for the 0.5. 8 diode control circuit
Update
: 2025-02-01
Size
: 1kb
Publisher
:
胡志伟
Quartus4
Downloaded:0
1 to achieve the six digital control circuit 2, six serial digital scanning tube rolling display circuit
Update
: 2025-02-01
Size
: 1kb
Publisher
:
胡志伟
VHDLSPI
Downloaded:0
SPI FOR FPGA COMMUNICATION
Update
: 2025-02-01
Size
: 1kb
Publisher
:
zhengguang
VHDL
Downloaded:0
VHDL example of 100 cases of common procedures covered basically the rich common example
Update
: 2025-02-01
Size
: 227kb
Publisher
:
zhengguang
verilog_soft
Downloaded:0
verilog_soft learning materials learning materials verilog_soft learning materials verilog_soft
Update
: 2025-02-01
Size
: 169kb
Publisher
:
tang
Verilog_tutorial
Downloaded:0
Contact Verilog_tutorial contact Verilog_tutorial guidance guidance guidance Verilog_tutorial Contact
Update
: 2025-02-01
Size
: 578kb
Publisher
:
tang
DE2_LCM_CCD
Downloaded:0
DE2 CCD digital camera source code, you can use to download. Facilitate learning.
Update
: 2025-02-01
Size
: 357kb
Publisher
:
张曦
RSC
Downloaded:0
Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
Update
: 2025-02-01
Size
: 1kb
Publisher
:
sunhao
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.23
.24
.25
.26
.27
3628
.29
.30
.31
.32
.33
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4311
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