VHDL-FPGA-Verilog List Page 3663

VHDL-FPGA-Verilog list

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sevensegment Downloaded：1: FPGA-Seven segment and counter
Update : 2025-01-31 Size : 356kb Publisher : obd
LCD Downloaded：0: LCD Interface Xilinx CPLD
Update : 2025-01-31 Size : 1.89mb Publisher : huangxing
vhdl Downloaded：0: Bcd nixie tube reality code
Update : 2025-01-31 Size : 3kb Publisher : taoli
LEDjun Downloaded：0: 4*4 multiply which can be used that s all.
Update : 2025-01-31 Size : 360kb Publisher : 赵伟
uart_verilog Downloaded：0: Serial port of the Verilog source code can be carried out under the modelsim simulation debugging
Update : 2025-01-31 Size : 9kb Publisher : huangguilin
mc8051_design Downloaded：0: 8051-core design, using Verilog hardware description language, in the modelsim simulation environment.
Update : 2025-01-31 Size : 387kb Publisher : huangguilin
cadence_allegro_teach Downloaded：0: CADENCE done using VHDL language course experiment
Update : 2025-01-31 Size : 1.2mb Publisher : fuchw
VHDL Downloaded：0: Verilog
Update : 2025-01-31 Size : 1.85mb Publisher : kudi5566
UART Downloaded：0: Hardware Design with VHDL Design Example: UART
Update : 2025-01-31 Size : 53kb Publisher : j
7-segment Downloaded：0: VHDL Design of BCD to 7-segment decoder using PROM
Update : 2025-01-31 Size : 59kb Publisher : FATIMA
motorcontrol(vhdl) Downloaded：0: FPGA-based servo system direct the design of the electrical code, VHDL language. Including feed-forward control, AD1674 control module, ADC0809 control module, feed-forward control module, such as sub-frequency modules.
Update : 2025-01-31 Size : 6kb Publisher : dong
cymomete Downloaded：0: Frequency measurement method used to design an 8-bit decimal figures show that the digital frequency meter. Measuring range 1-499999hz.
Update : 2025-01-31 Size : 1kb Publisher : dong

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