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VHDL-FPGA-Verilog list
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CRC
Downloaded:0
CRC code. . . . . . . . . . . . . . . . .
Update
: 2025-01-31
Size
: 1kb
Publisher
:
lzndcb
s
Downloaded:0
Beverage vending machine. . . . . . . . . . . . . . . . . . .
Update
: 2025-01-31
Size
: 1kb
Publisher
:
lzndcb
20074621282517
Downloaded:0
Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and fin
Update
: 2025-01-31
Size
: 4kb
Publisher
:
老毕
quanjiaqi
Downloaded:0
Way flow of 4 full adder 8. . . . . .
Update
: 2025-01-31
Size
: 1kb
Publisher
:
lzndcb
ds18b20
Downloaded:1
Introduction ds18b20 and timing, as well as read and write ds18b20 temperature vhdl procedure quartus compiled simulation environment
Update
: 2025-01-31
Size
: 14kb
Publisher
:
dreamy
4
Downloaded:0
VHDL Waveform Generator and Simulation of VHDL procedures
Update
: 2025-01-31
Size
: 2kb
Publisher
:
佚名
edaCourseware
Downloaded:0
include Courseware about eda
Update
: 2025-01-31
Size
: 3.04mb
Publisher
:
王宏
Cymometer_of_four_decimal
Downloaded:0
Four decimal digital frequency meter: measuring range: 1Hz ~ 10kHz show that no less than 1S with memory function showed that the course set in the measurement data, and so on until the end of the measurement results sho
Update
: 2025-01-31
Size
: 3kb
Publisher
:
Verilog
Downloaded:0
it is good information for FPGA
Update
: 2025-01-31
Size
: 153kb
Publisher
:
王红勤
soldervhdl
Downloaded:0
Vhdl program for vending machine
Update
: 2025-01-31
Size
: 7kb
Publisher
:
dreamy
CycloneDeviceHandbookVolume
Downloaded:0
This is a FPGA cyclone on the data sheet.
Update
: 2025-01-31
Size
: 3.18mb
Publisher
:
许健
ram_2561
Downloaded:0
This is what I wrote it myself a little VERILOG procedures, on the creation of a 256 number.
Update
: 2025-01-31
Size
: 151kb
Publisher
:
许健
«
1
2
...
.65
.66
.67
.68
.69
3670
.71
.72
.73
.74
.75
...
4311
»
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