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VHDL-FPGA-Verilog list
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32bit carry select adder
Update : 2025-01-31 Size : 1kb Publisher : suha

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this is the vhdl code of arithmetic and logic unit of 16 bit microprocessor.
Update : 2025-01-31 Size : 145kb Publisher : Anshul

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this is a 8 bit adder,
Update : 2025-01-31 Size : 155kb Publisher : 朱金涛

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Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilinx, Lattice, Altera and other manufacturers of the CPLD/FPGA.
Update : 2025-01-31 Size : 3.08mb Publisher : 李德明

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The use of Xilinx XC2C128 (Xilinx CPLD) desktop computer system to do the Debug Card and schematic diagram for the motherboard does not boot, can detect the CPU to the Northbridge Flanagan signal line between the concret
Update : 2025-01-31 Size : 1.17mb Publisher : 李德明

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Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15 seconds if there is no pressing Key1, will be set automatically dial
Update : 2025-01-31 Size : 897kb Publisher : 李德明

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Binary to BCD converter
Update : 2025-01-31 Size : 1kb Publisher : Natacho

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Example of a FPGA memory controler
Update : 2025-01-31 Size : 7kb Publisher : Natacho

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VHDL language used to display the clock source code
Update : 2025-01-31 Size : 2kb Publisher : shulin

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ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
Update : 2025-01-31 Size : 852kb Publisher : 宋振丰

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Quartus2 programming environment in the VHDL language under 32* 32 high-speed computing
Update : 2025-01-31 Size : 1kb Publisher : CAR

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Based on the VHDL language, A/D sampling control procedures, procedures for the use of state machine to achieve the
Update : 2025-01-31 Size : 163kb Publisher : zhangzhen
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