VHDL-FPGA-Verilog List Page 3678

VHDL-FPGA-Verilog list

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TUT1_BASIC1_7C5TP Downloaded：0: FPGA-89S51IP core
Update : 2025-01-30 Size : 88kb Publisher : 邱柳钦
fifo Downloaded：0: VHDL language with code written in FIFO, FIFO depth can be set up
Update : 2025-01-30 Size : 1kb Publisher : wd
A_bit_serial_data_transmitter Downloaded：0: • To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify the correct behavi
Update : 2025-01-30 Size : 2kb Publisher : 吴德昊
CPLD_Implementation_of_a_Lucky_Dip_Machine Downloaded：0: Digital Electronic Design Automation Workshop on Rapid Prototyping using a CPLD Lucky Dip Machine using the Digilent X-Board
Update : 2025-01-30 Size : 4kb Publisher : 吴德昊
Heilbronn_Visit_Design Downloaded：0: Heilbronn Visit Design Digital Combination Lock
Update : 2025-01-30 Size : 4kb Publisher : 吴德昊
Pulse_Width_Modulator_Project Downloaded：0: Pulse-width modulation (PWM) of a signal or power source involves the modulation of its duty cycle, to either convey information over a communications channel or control the amount of power sent to a load.
Update : 2025-01-30 Size : 288kb Publisher : 吴德昊
TRL_Design_of_a_asynchronous_bit_serial_data_trans Downloaded：0: • To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of the transmitter by means
Update : 2025-01-30 Size : 2kb Publisher : 吴德昊
VHDL Downloaded：0: homework of VHDL course at SJTU
Update : 2025-01-30 Size : 6kb Publisher : caozizhong
shujiplj Downloaded：0: Jump dynamic, shifting the design of digital frequency meter, four range classes automatically!
Update : 2025-01-30 Size : 99kb Publisher : 陈媛
vhdl Downloaded：0: learning vhdl book a must-see. Absolute classic books
Update : 2025-01-30 Size : 17.05mb Publisher : 小哲
shifter Downloaded：0: SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change
Update : 2025-01-30 Size : 126kb Publisher : 623902748
EXERCISE_5_3_4_3 Downloaded：0: M for the clock pulse CLK mode control allow CO to enter into the S displacement control mode shift 0-3 D [7 .. 0] is the data input shift QB [7 .. 0] is the data output shift CN is a binary data output shift
Update : 2025-01-30 Size : 1.38mb Publisher : 623902748

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