VHDL-FPGA-Verilog List Page 3682

VHDL-FPGA-Verilog list

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count999 Downloaded：0: achieved vhdl counter, can be recorded from 0 to 999, the code uses the modular design concept, development tools muxplus2
Update : 2025-01-29 Size : 201kb Publisher : gmaj
8-way-control-lantern Downloaded：0: 8 subject lantern-type shift registers require two flower type, respectively, the experimental realization of the two flower types, it is designed mainly as 74,194 then twisting the ring structure to achieve the shift re
Update : 2025-01-29 Size : 1kb Publisher : 周游
taxibillingsystemVerilog Downloaded：0: In Quartus II 5.0 environment, the development of the taxi billing system can be of different situations on the taxi billing, accurate to 0.5 yuan
Update : 2025-01-29 Size : 954kb Publisher : 赵小川
WindowsApplication1 Downloaded：0: VERY EASY
Update : 2025-01-29 Size : 14kb Publisher : Danny
second Downloaded：0: On the stopwatch to write VHDL procedures modules, top-level documents, for reference only
Update : 2025-01-29 Size : 467kb Publisher : 娃娃
crc16 Downloaded：0: crc16 module for SDIO DAT line calculation
Update : 2025-01-29 Size : 1kb Publisher : kantengri
ncr Downloaded：0: module to wait 2 clocks for SD card
Update : 2025-01-29 Size : 1kb Publisher : kantengri
wait_data Downloaded：0: module to wait data on DAT line SDIO mode
Update : 2025-01-29 Size : 1kb Publisher : kantengri
send_cmd Downloaded：0: SD card SDIO module send command and read response
Update : 2025-01-29 Size : 1kb Publisher : kantengri
FiltroDSP Downloaded：0: This sources implement a 8-bit FIR Filter with selectable coefficent rom.
Update : 2025-01-29 Size : 1.51mb Publisher : Jose
MultiplicadorSHIF Downloaded：0: This code creates a 8 bit full multiplier.
Update : 2025-01-29 Size : 1.34mb Publisher : Jose
dds Downloaded：0: The use of EDA hardware description language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
Update : 2025-01-29 Size : 727kb Publisher : 游智超

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