VHDL-FPGA-Verilog List Page 3816

VHDL-FPGA-Verilog list

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vhdl_clock Downloaded：0: VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function
Update : 2025-01-21 Size : 7kb Publisher : 孙超
2-QUARTUSII Downloaded：0: Let us be more understanding of EDA technology in daily life importance.
Update : 2025-01-21 Size : 549kb Publisher : 马剑
multiplyingunit Downloaded：0: Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the left after the first and add if for 0, the left
Update : 2025-01-21 Size : 134kb Publisher : 张华
sin125 Downloaded：0: Using FPGA to achieve DDS signal generator (sine wave 125kHz)
Update : 2025-01-21 Size : 192kb Publisher : 杜海明
serial Downloaded：0: VHDL-based serial communication based on VHDL Serial Communication
Update : 2025-01-21 Size : 369kb Publisher : 戴明
USB11Core Downloaded：0: FPGA design USB1.1IP Core, documentation is also inside the
Update : 2025-01-21 Size : 892kb Publisher : why
EEPROM_RD_WR Downloaded：0: This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM com
Update : 2025-01-21 Size : 107kb Publisher : 周
VerilogHDL Downloaded：0: Based on VerilogHDL Practical Guide, a book to introduce easy-to-read
Update : 2025-01-21 Size : 3.37mb Publisher : xiaoxiao
11 Downloaded：0: VHDL syntax support is not the same as the scope, the following procedures for some of the statements may not be able to run on all of the software platform, so the procedure may have to make some changes, at the same ti
Update : 2025-01-21 Size : 1kb Publisher : 夏巍
22 Downloaded：0: VHDL language to achieve three of the voting machine control circuit, a priority setting features such as autonomous
Update : 2025-01-21 Size : 1kb Publisher : 夏巍
ug_lpm_rom Downloaded：0: quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
Update : 2025-01-21 Size : 805kb Publisher : 王欣欣
ug_memrom Downloaded：0: Quartus joint simulation with MATLAB to generate rom table,
Update : 2025-01-21 Size : 1.18mb Publisher : 王欣欣

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