VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function Update : 2025-03-17
Size : 7kb
Publisher : 孙超
Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the left after the first and add if for 0, the left Update : 2025-03-17
Size : 134kb
Publisher : 张华
This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM com Update : 2025-03-17
Size : 107kb
Publisher : 周
VHDL syntax support is not the same as the scope, the following procedures for some of the statements may not be able to run on all of the software platform, so the procedure may have to make some changes, at the same ti Update : 2025-03-17
Size : 1kb
Publisher : 夏巍
VHDL language to achieve three of the voting machine control circuit, a priority setting features such as autonomous Update : 2025-03-17
Size : 1kb
Publisher : 夏巍