VHDL-FPGA-Verilog List Page 3821

VHDL-FPGA-Verilog list

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Lift Downloaded：0: VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
Update : 2025-01-21 Size : 752kb Publisher : 许昕
VGA_driver_verilog Downloaded：0: Based on Verilog HDL design of the VGA driver
Update : 2025-01-21 Size : 58kb Publisher : 蓝色的海
led_display Downloaded：0: Verilog HDL-based design flow lights
Update : 2025-01-21 Size : 7kb Publisher : 蓝色的海
verilog_led Downloaded：0: Verilog HDL-based digital control programming
Update : 2025-01-21 Size : 83kb Publisher : 蓝色的海
CAN_Bus_basis Downloaded：1: Based on the CAN bus automotive simulation. Automotive examples for the public Touran. A resolution of 1024x768.
Update : 2025-01-21 Size : 224kb Publisher : 张宇
newSD Downloaded：0: Based on a complete Verilog timing SDRAM controller code
Update : 2025-01-21 Size : 4kb Publisher : 云
dattransf Downloaded：0: VHDL-based set of 10 points to float the source code modules can be integrated
Update : 2025-01-21 Size : 2kb Publisher : 云
dcm2 Downloaded：0: Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
Update : 2025-01-21 Size : 1kb Publisher : 云
fifoi Downloaded：0: Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
Update : 2025-01-21 Size : 2kb Publisher : 云
qudou Downloaded：0: Generic VHDL-based state machine keys and signal to the jitter module, very useful
Update : 2025-01-21 Size : 1kb Publisher : 云
cd Downloaded：0: 1 in the process of testing the clock rising edge, cycle accumulate, triggering the process of 2, a high output, so that LED lamp
Update : 2025-01-21 Size : 1kb Publisher : 张力
COUNTER Downloaded：0: External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
Update : 2025-01-21 Size : 1kb Publisher : fsdfe

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