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VHDL-FPGA-Verilog list
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53lift
Downloaded:0
5,3 wavelet few on FPGA hardware implementation of the articles, very helpful
Update
: 2025-01-20
Size
: 1.32mb
Publisher
:
微微蓝
fcsr
Downloaded:0
Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Update
: 2025-01-20
Size
: 1kb
Publisher
:
李辛
ffcsr
Downloaded:0
Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Update
: 2025-01-20
Size
: 2kb
Publisher
:
李辛
mux
Downloaded:0
MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
Update
: 2025-01-20
Size
: 117kb
Publisher
:
张应辉
paobiao
Downloaded:0
Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quartus II development of the process of di
Update
: 2025-01-20
Size
: 232kb
Publisher
:
张应辉
fpga-plus
Downloaded:0
FPGA on the slide, very useful to explain. Mainly related to fpga-plus kinds of knowledge.
Update
: 2025-01-20
Size
: 1.17mb
Publisher
:
xiao yu
alu
Downloaded:0
Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
Update
: 2025-01-20
Size
: 1kb
Publisher
:
helen
a
Downloaded:0
ADPLL of high level phase locked loop
Update
: 2025-01-20
Size
: 1.4mb
Publisher
:
bc
rs232_rec5
Downloaded:0
Update
: 2025-01-20
Size
: 529kb
Publisher
:
111
Downloaded:0
51 Single-chip design of the electronic code lock
Update
: 2025-01-20
Size
: 11kb
Publisher
:
张明明
pll
Downloaded:0
Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Update
: 2025-01-20
Size
: 9.61mb
Publisher
:
gk
USB
Downloaded:0
USB source code, based on the VHDL language, verified in QuartusII above its function
Update
: 2025-01-20
Size
: 5kb
Publisher
:
周
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4311
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