VHDL-FPGA-Verilog List Page 3864

VHDL-FPGA-Verilog list

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VHDL-SPI-Module.doc Downloaded：0: The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an exte
Update : 2025-01-20 Size : 37kb Publisher :
tt Downloaded：0: This is a VHDL hardware description language written by a program, and hopes that the results of simulation and then look at the output!
Update : 2025-01-20 Size : 18kb Publisher : zhanhui
Verilog_Coding_for_Logic_Synthesis Downloaded：0: Can be integrated Verilog coding, very good, a must-see learning Verilog. Not to be missed
Update : 2025-01-20 Size : 1.1mb Publisher : Benson
chuanbingvhdl Downloaded：0: Because most of the computer using a serial device, the program realization of digital circuits used in serial input parallel output function.
Update : 2025-01-20 Size : 1kb Publisher : yifang
alu_16 Downloaded：1: Three 16-bit integer arithmetic logic unit of the ALU design methodology, called library function 74181 (4 ALU), composed of serial 16-bit arithmetic logic unit. (With 74,181 positive logic) B. Call library functions 741
Update : 2025-01-20 Size : 1kb Publisher : yifang
crcm Downloaded：0: CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Update : 2025-01-20 Size : 1kb Publisher : fangliang
rec Downloaded：0: Use FPGA to achieve synchronous serial port, experience, certified, for your reference
Update : 2025-01-20 Size : 1kb Publisher : fangliang
ViterbiDecodeK9R12HardDecision Downloaded：0: hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
Update : 2025-01-20 Size : 12kb Publisher : maojunling
dff Downloaded：0: VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
Update : 2025-01-20 Size : 1kb Publisher : daniel
Verilog Downloaded：0: Digital Circuit Design Guide, veriloghdl Design
Update : 2025-01-20 Size : 165kb Publisher : 段晋杰
EP3C25 Downloaded：0: Cyclone 庐 III EP3C25 information
Update : 2025-01-20 Size : 515kb Publisher : 杨洋
DE2_VGA3 Downloaded：0: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the c
Update : 2025-01-20 Size : 1.22mb Publisher : Donghua Gu

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