VHDL-FPGA-Verilog List Page 3944

VHDL-FPGA-Verilog list

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verilog100 Downloaded：0: More than 100 examples of good learning materials Verilog, you can a lot of reference, suitable for beginners to learn
Update : 2025-01-17 Size : 4.45mb Publisher : mermaid
dds Downloaded：0: DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Update : 2025-01-17 Size : 1.31mb Publisher : 谭儆轩
SIGNAL_ALL Downloaded：0: Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation
Update : 2025-01-17 Size : 3.26mb Publisher : 谭儆轩
0522 Downloaded：0: Their own design this year
Update : 2025-01-17 Size : 1.31mb Publisher : dawn
uart Downloaded：0: FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
Update : 2025-01-17 Size : 4.86mb Publisher : 吕常智
clr_m Downloaded：0: Using FPGA to achieve some of the fuzzy controller using VHDL source code prepared
Update : 2025-01-17 Size : 1kb Publisher : 林
div16_8 Downloaded：0: Realize the fuzzy controller with FPGA using VHDL language part of the source
Update : 2025-01-17 Size : 1kb Publisher : 林
datacont Downloaded：0: The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requi
Update : 2025-01-17 Size : 316kb Publisher : 王思
DA_FIR Downloaded：0: Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Update : 2025-01-17 Size : 519kb Publisher : CH
wtut_vhd Downloaded：0: On the stopwatch design, in great detail, including the test documents, has been through simulation. For reference
Update : 2025-01-17 Size : 34kb Publisher : 邢继元
wtut_ver Downloaded：0: verilog HDL language digital stopwatch, simulation has already been adopted, for reference
Update : 2025-01-17 Size : 26kb Publisher : 邢继元
uart_exam Downloaded：0: Written in VHDL serial, very good, and the procedure is very simple, you can debug with
Update : 2025-01-17 Size : 1kb Publisher : jimmy

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