VHDL-FPGA-Verilog List Page 3955

VHDL-FPGA-Verilog list

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ByteBlasterII Downloaded：0: Introduction ByteBlastrII (FPGA download circuit interface) circuit design, in accordance with circuit design, has been tried, can be used. Finally got the. Altera download original line does sell more than 1K
Update : 2025-01-17 Size : 120kb Publisher : sun huaiming
verilog Downloaded：0: This is the Verilog hardware description language learning essential classic.
Update : 2025-01-17 Size : 458kb Publisher : 田园
ref-sqroot Downloaded：0: The square root of IP will be open sqroot_license.txt in FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING = gl15kdhm5gUPkJD7iM82mn $ $ HOSTID = ANY can be used to join!
Update : 2025-01-17 Size : 39kb Publisher : lin
rece_7E Downloaded：0: HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Update : 2025-01-17 Size : 2kb Publisher : 刘彻
vhdlsample Downloaded：0: VHDL example of many, many examples of VHDL,
Update : 2025-01-17 Size : 165kb Publisher : aaa
VHDL_8051 Downloaded：0: Use VHDL to write a 8051 core, and they hope to learn IC design Tongren help.
Update : 2025-01-17 Size : 394kb Publisher : king
VHDL_UART Downloaded：0: VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on.
Update : 2025-01-17 Size : 3kb Publisher : liukun
VHDL_VGA Downloaded：0: The source files are stored in the SRC directory, and the project files of QII are stored in the Proj directory; The function of the program is to display color stripes on the VGA display, with 8 colors
Update : 2025-01-17 Size : 243kb Publisher : liukun
1 Downloaded：0: : Frequency meter. With four shows that will automatically count seven decimal results, automatic selection of high-effective data for dynamic display 4. Express the decimal point is 1000, that is, KHz.
Update : 2025-01-17 Size : 1kb Publisher : 张伯伦
9999counter Downloaded：0: -- 9999 counter module 4 output The design request frequency meter is shown in four paragraphs. Therefore, the counter USES 0~ 9999 counting, which can make good use of the digital tube and increase the accuracy of the f
Update : 2025-01-17 Size : 1kb Publisher : 张伯伦
4 Downloaded：0: Control module is the core of Cymometer with features as described below: The input data to determine and output stall signals - 10KHZ highest for 1010, for high-grade, the lowest for 0000, the decimal point does not shi
Update : 2025-01-17 Size : 2kb Publisher : 张伯伦
shuzizhong Downloaded：0: Digital Clock code using VHDL language to design a digital clock system, which has a display hours, minutes and seconds functions, when a more functional, with the whole point timekeeping function.
Update : 2025-01-17 Size : 1kb Publisher : SDFG

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