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VHDL-FPGA-Verilog list
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fifo-
Downloaded:0
Asynchronous fifo design documents, can look at those who need it.
Update
: 2025-01-17
Size
: 140kb
Publisher
:
陈强
cuart
Downloaded:0
On the UART
Update
: 2025-01-17
Size
: 5kb
Publisher
:
曙光
pn
Downloaded:1
Verilog language used to generate seven small m sequence code generated pn
Update
: 2025-01-17
Size
: 2kb
Publisher
:
楚鹤
jtag_logic
Downloaded:0
This is the CPLD program used by homebrew altera usb_blaster, written in VHDL language.
Update
: 2025-01-17
Size
: 2kb
Publisher
:
wdy2004
ok1
Downloaded:0
Using VHDL language ps2 keyboard identification procedures, and output to 8* 8 matrix display
Update
: 2025-01-17
Size
: 1kb
Publisher
:
sclzcq
RISC_Core
Downloaded:0
This described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
Update
: 2025-01-17
Size
: 309kb
Publisher
:
wdy2004
fsm
Downloaded:0
Very good introduction FSM needs to look at, or good
Update
: 2025-01-17
Size
: 186kb
Publisher
:
刘峰
diantikongzhiqi
Downloaded:0
The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of wav
Update
: 2025-01-17
Size
: 67kb
Publisher
:
polly
ballgame
Downloaded:0
Using VHDL language pinball game, control baffle bounce on the screen to catch the ball. Show the output as a standard VGA signal, can be directly connected to VGA displays. QuartusII available in software downloaded to
Update
: 2025-01-17
Size
: 3kb
Publisher
:
Guo Deyuan
LFSR
Downloaded:0
Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Update
: 2025-01-17
Size
: 159kb
Publisher
:
zx
brentkung_adder
Downloaded:0
Synopsys
Update
: 2025-01-17
Size
: 510kb
Publisher
:
zx
simu_NIOS
Downloaded:0
NIOS function and the same CPU, the FPGA can run, Verilog source code
Update
: 2025-01-17
Size
: 52kb
Publisher
:
zx
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3957
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