VHDL-FPGA-Verilog List Page 3997

VHDL-FPGA-Verilog list

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LVDS Downloaded：0: LVDS design for example to study the timing analysis ISE as well as the use of low-level device layout method in the bottom of the layout of LVDS device pin to bound methods, the bottom of the layout design flow, the und
Update : 2025-01-16 Size : 126kb Publisher : 程凯
ddswase Downloaded：0: dds signal generator, can generate any frequency of the sine wave, the waves and harmonics. has been compiled through
Update : 2025-01-16 Size : 2kb Publisher :
suocun Downloaded：0: vhdl3 frequency function names look know, but also with what you say, we are all smart people
Update : 2025-01-16 Size : 34kb Publisher : fql984722
FPGA Downloaded：0: HDTV video content creation and prosperity as well as bandwidth-constrained environment of the broadcasting channel to send video content of these methods, birth of a new video compression standards and associated video
Update : 2025-01-16 Size : 58kb Publisher : chenqunqin
fifo-1117 Downloaded：0: This is the asynchronous FIFO realize the VHDL code, the FPGA has been proved through practice, running in good condition
Update : 2025-01-16 Size : 20kb Publisher : 杨宇
ditie Downloaded：0: To a complete state machine to realize automatic ticket vending machines all the features, so the design is more convenient, do not slice production. But the drawback is that the actual function will be some impact (devi
Update : 2025-01-16 Size : 16kb Publisher : zsb
fdct Downloaded：0: Anti-cosine transform Verilog coding algorithm, tested through
Update : 2025-01-16 Size : 3kb Publisher : zsb
ro_cnt Downloaded：0: Small counter coding, the use of Verilog language, have been tested through
Update : 2025-01-16 Size : 1kb Publisher : zsb
MCU Downloaded：0: Ultrasonic Distance Measurement Sensor- How to DIY a part of your ultrasonic range finder.
Update : 2025-01-16 Size : 20kb Publisher : 吴敏之
dctub11 Downloaded：0: Discrete Cosine Transform transform modules, verilog language, and through functional simulation
Update : 2025-01-16 Size : 1kb Publisher : zsb
16lift2vhdl Downloaded：0: This is a 16-story elevator control system. Now for everyone to share, if not good. Please do not stock.
Update : 2025-01-16 Size : 2kb Publisher : 高建军
VGA_1024×768×85 Downloaded：0: Using verilog hdl realize the VGA display color signals, including VGA timing, vertical color, Wang Cai, the checkerboard lattice
Update : 2025-01-16 Size : 440kb Publisher : 华磊

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