VHDL-FPGA-Verilog List Page 4031

VHDL-FPGA-Verilog list

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chk Downloaded：0: This procedure implements a sequence detector. When a string of serial data to be tested after entering the detector, if the number in each successive detection with the same number of preset password, then output A , ot
Update : 2025-01-15 Size : 1kb Publisher : liushenshen
VHDL Downloaded：0: Xi an Polytechnic very useful information, suitable for beginners
Update : 2025-01-15 Size : 833kb Publisher : 马雷
chengxu Downloaded：0: MaxplusII used in the VHDL language programming realization of digital base-band signal synchronization extraction, is a password input and modify the examples. Experimental box in the hardware connection, and will downl
Update : 2025-01-15 Size : 760kb Publisher : 李磊
ADcaiyang Downloaded：0: A/D sampling control module designed A/D sampling control modules responsible for controlling external ADC0809 chip multi-channel analog input, as well as the amount of strobe to achieve A/D sampling the reasonable contr
Update : 2025-01-15 Size : 1kb Publisher : xuye
UARTRS232 Downloaded：0: Using UART to receive PC-RS232 serial interface data. As the UART receive only 8-bit data, so to receive two 8-bit data after its deposit in 16 of the SRAM.
Update : 2025-01-15 Size : 1kb Publisher : xuye
1 Downloaded：0: Adder VHDL code can be applied directly in many places
Update : 2025-01-15 Size : 1kb Publisher : stormy
16szxgq Downloaded：1: 16-bit digital correlator through four and four correlator adder circuit composed of two
Update : 2025-01-15 Size : 1kb Publisher : zh
RotaryEncoderInterfaceForSPARTAN-3E Downloaded：1: SPARTAN-3E Starter board example, using the left knob to control LED
Update : 2025-01-15 Size : 392kb Publisher : zhuxuopeng
eth_ocm Downloaded：0: sopc builder of networks of nuclear eth_ocm
Update : 2025-01-15 Size : 233kb Publisher : 1984taozi
i2c_p_altera Downloaded：0: altera i2c slave ip to prepare nuclear Verilog
Update : 2025-01-15 Size : 1.51mb Publisher : 1984taozi
qiangdaqi Downloaded：0: Answer to achieve function, 30 seconds of the countdown for the Answer can be controlled,
Update : 2025-01-15 Size : 238kb Publisher : 涂亮
fftvhdl Downloaded：0: VHDL language used to achieve the FFT source code, so that the procedure, we try. QUARTUS II software development
Update : 2025-01-15 Size : 28kb Publisher : 王真

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