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VHDL-FPGA-Verilog list
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err
Update : 2025-01-15 Size : 1kb Publisher : wx

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Sine wave generator, VHDL applications and processing, can generate arbitrary waveform
Update : 2025-01-15 Size : 1.65mb Publisher : WBT

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VHDL hardware description, the use of the environment Quartus2 6.1, respectively, for 16 M and 60 M-ary counter source code
Update : 2025-01-15 Size : 255kb Publisher : 保密

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Efficient structure of multi-input floating-point multiplier in FPGA Implementation
Update : 2025-01-15 Size : 137kb Publisher : stormy

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Verilog description of date, hours minutes and seconds display, from 2000 to 2099 million in the calendar year cycle with set control, set the status, click to change a setting, the normal display, press set to enter the
Update : 2025-01-15 Size : 4kb Publisher : 申刚

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Verilog description 23:59:59-00:00:00 since by timer set by the key, enter the settings, followed by reverse-time, hours, minutes, seconds set, and then have access to reverse time, in the direction of time, and by Timme
Update : 2025-01-15 Size : 2kb Publisher : 申刚

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Dressing a third-order filter (CIC) of the VHDL source code
Update : 2025-01-15 Size : 1kb Publisher : 白杨

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Using VHDL realization fsk modulated signal, the input signal can be used random code.
Update : 2025-01-15 Size : 1kb Publisher : 白杨0129

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LCD_test. To test the LCD display. Has been used in the DE2 Development Office, and can be used
Update : 2025-01-15 Size : 4kb Publisher : teok

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Asynchronous serial port communications design example, it is practical. Comparison of the classic.
Update : 2025-01-15 Size : 482kb Publisher : 王网

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Verilog realization of LED control, dynamic refresh display 210. LED display control procedure template
Update : 2025-01-15 Size : 102kb Publisher : 张猛蛟

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4 Enter a binary number, use the dial code switches that make light-emitting diodes show the four binary number.
Update : 2025-01-15 Size : 202kb Publisher : fishafish
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