VHDL-FPGA-Verilog List Page 4047

VHDL-FPGA-Verilog list

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i2c_S Downloaded：0: I2C Slave module The module contains N accessable Registers when in read Process, all Registers are read at a time when in write Process, only the addressed register are Writeable.
Update : 2025-01-13 Size : 2kb Publisher : 李全
Libero8.0 Downloaded：0: Libero8.0_ tutorial, I hope to learn the FPGA can be to help the students.
Update : 2025-01-13 Size : 3.64mb Publisher : 江鹏
AHDL Downloaded：0: AHDL basic language, useful for beginners Kazakhstan, can design a simple circuit
Update : 2025-01-13 Size : 2.14mb Publisher : chenfang
DE2_NIOS_DEVICE_LED Downloaded：0: NIOSII debug procedures, suitable experimental and other related DE2 board
Update : 2025-01-13 Size : 2.78mb Publisher : jemalyang
WritingTestbenches Downloaded：0: Testbench prepared super good tutorials, on-line this information is relatively small. (Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf
Update : 2025-01-13 Size : 3.92mb Publisher : 文成
Verilog Downloaded：0: Ultra-detailed tutorials Verilog digital IC design entry to the territory from the HDL, the Department of Microelectronics, Peking University, in mts ppt
Update : 2025-01-13 Size : 1.48mb Publisher : 文成
CICdeVHDL Downloaded：0: I prepared three Extractor of VHDL code, available for reference for everyone and, if inappropriate, also requested the exhibitions.
Update : 2025-01-13 Size : 1kb Publisher : 谢白玉
division5 Downloaded：0: 5 times the frequency of the VHDL code, validated the code is correct, and have been used.
Update : 2025-01-13 Size : 1kb Publisher : 谢白玉
renyifenpin Downloaded：0: Arbitrary frequency of VHDL realize that if the needs of specific parameters, simply change the process parameters of the sub-band can be realized.
Update : 2025-01-13 Size : 1kb Publisher : 谢白玉
p2s16_1 Downloaded：0: Some time ago to see someone in the online order and string conversion procedures, idle today, and on the allocation of a reference for everyone. In fact, it is very simple, as long as the ideas sorted out, or very easy.
Update : 2025-01-13 Size : 1kb Publisher : 谢白玉
erfenpindevhdlyuveriloghdl Downloaded：0: This is on 2-of VHDL and verilog hdl realize realize, have been made to verify the correctness of simulation, we can contrast reference.
Update : 2025-01-13 Size : 1kb Publisher : 谢白玉
ADD_Float_IEEE754 Downloaded：0: IEEE754 floating point adder
Update : 2025-01-13 Size : 6kb Publisher : 洪瑞徽

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